Scalable multimedia platform architecture

• US 5,335,321 A
• Filed: 06/19/1992
• Issued: 08/02/1994
• Est. Priority Date: 06/19/1992
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Lippincott, Louis A., Harney, Kevin
• Primary Examiner(s): Shaw, Dale M.
• Assistant Examiner(s): Tung, Kee M.
• Application Number:
  US07/901,383
• Time in Patent Office: 774 Days
• Field of Search: 395/154, 395/153, 395/162, 395/163, 395/164, 395/275, 340/721, 340/798-800, 345/112, 345/189, 345/2, 345/204
• US Class Current: 345/503
• CPC Class Codes: G06F 13/423 with synchronous protocol
• CPC Class Codes: G06F 3/14 Digital output to display device ; Cooperation and interconnection of the display device with other functional units
• CPC Class Codes: G09G 5/363 Graphics controllers

Abstract

The scalable platform architecture of the present video processing system invention includes a bus for transmitting data between various video processing subsystems. A graphics processing subsystem is coupled to the bus. A central processing unit is coupled to the bus and performs video processing. The graphics processing subsystem is adapted to receive a video memory and to perform video processing when the video memory is received. The bus is provided with expansion connectors for detachably coupling to a video processing subsystem and a video capture system. The addition of the video processing subsystem and/or video capture subsystem accelerates the processing of the video processing system by performing video processing that would otherwise be performed by the central processing unit.

Claims

1. A video processing system comprising:

bus means for transmitting data;

graphics processing means coupled to said bus means for performing graphics processing;

a central processing unit coupled to said bus means and for performing video processing;

first connecting means for detachably receiving a video acceleration subsystem for performing video processing and electrically coupling said bus means to said video acceleration subsystem, wherein said video acceleration subsystem accelerates said video processing system by performing at least some of the video processing otherwise performed by said central processing unit; and

second connecting means for detachably receiving a video capture subsystem for performing video capture processing and for electrically coupling said bus means to said video capture subsystem, wherein said video capture subsystem accelerates said video processing system by performing video capture processing otherwise performed by said central processing unit.

2. The video processing system of claim 1, wherein said graphics processing means comprises:

means for detachably receiving and electrically coupling to a video memory; and

means for performing video processing when said video memory is coupled to said graphics processing means.

3. A video processing system comprising:

bus means for transmitting data;

graphics processing means coupled to said bus means for performing graphics processing;

a central processing unit coupled to said bus means and for performing video processing;

first connecting means for detachable receiving a video acceleration subsystem for performing video processing and electrically coupling said bus means to said video acceleration subsystem, wherein said video acceleration subsystem accelerates said video processing system by performing at least some of the video processing otherwise performed by said central processing unit; and

second connecting means for detachably receiving a video capture subsystem for performing video capture processing and for electrically coupling said bus means to said video capture subsystem.

4. The video processing system of claim 3, wherein said graphics processing means comprises:

means for detachably receiving and electrically coupling to a video memory; and

means for performing video processing when said video memory is coupled to said graphics processing means.