Multiprocessor cache snoop access protocol wherein snoop means performs snooping operations after host bus cycle completion and delays subsequent host bus cycles until snooping operations are completed

• US 5,335,335 A
• Filed: 08/30/1991
• Issued: 08/02/1994
• Est. Priority Date: 08/30/1991
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Compaq Computer Corporation (HP Inc.)
• Inventors: Tipley, Roger E., Stevens, Jeffrey C., Jackson, Mike T.
• Primary Examiner(s): Dixon, Joseph L.
• Assistant Examiner(s): Asta, Frank J.
• Application Number:
  US07/753,420
• Time in Patent Office: 1,068 Days
• Field of Search: 395/400, 395/425, 364/200 MS File, 364/900 MS File
• US Class Current: 711/121
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means

Abstract

A method and apparatus for enabling a dual ported cache system in a multiprocessor system to guarantee snoop access to all host bus cycles which require snooping. The cache controller includes a set of latches coupled to the host bus which it uses to latch the state of the host bus during a snoop cycle if the cache controller is unable to immediately snoop that cycle. The cache controller latches that state of the host bus in the beginning of a cycle and preserves this state throughout the cycle due to the effects of pipelining on the host bus. In addition, the cache controller is able to delay host bus cycles to guarantee snoop access to host bus cycles which require snooping. The cache controller generally only delays a host bus cycle when it is already performing other tasks, such as servicing its local processor, and cannot snoop the host bus cycle immediately. When the cache controller latches the state of the bus during a write cycle, it only begins to delay the host bus after a subsequent cycle begins. In this manner, one write cycle can complete on the host bus before the cache controller delays any cycles, thereby reducing the impact of snooping on host bus bandwidth. Read cycles are always delayed until the cache controller can complete the snooping operation because the cache may be the owner of the data and a write back cycle may be necessary.

Claims

1. A computer system having guaranteed cache controller snoop access, the computer system comprising:

a host bus having a state when a cycle is executing;

random access memory coupled to said host bus;

one or more microprocessors coupled to said host bus; and

at least one other device coupled to said host bus for performing cycles on said host bus;

wherein, each of said microprocessors has an associated cache memory and cache controller coupled to said host bus for performing cycles on said host bus, each of said cache controllers snooping said host bus while other cache controllers and other devices are performing cycles on said host bus which require snooping, said cache controllers including;

means coupled to said host bus for latching the state of said host bus during a host bus cycle; and

means coupled to said latching means for snooping said host bus cycle from said latched host bus state after said host bus cycle is no longer present on said host bus.

2. The computer system of claim 1, wherein said snooping means snoops said latched host bus state after said host bus cycle has completed if said host bus cycle is a write cycle and said snooping means has not snooped said latched host bus state before said host bus cycle completes.

3. The computer system of claim 2, said cache controller further comprising:

means coupled to said host bus and said snooping means for delaying completion of a subsequent cycle after a write cycle if said snooping means has not yet snooped said latched host bus state.

4. The computer system of claim 3, wherein said delaying means delays completion of said subsequent host bus cycle until said snooping means snoops said latched host bus state.

5. The computer system of claim 4, wherein the computer system further includes a memory controller coupled to said host bus and said random access memory for controlling accesses of said random access memory, and wherein the computer system includes a means coupled to the host bus which generates a ready signal to complete host bus cycles;

and

wherein said delaying means provides a signal to said ready signal generating means which prevents said ready signal generating means from generating said ready signal.

6. The computer system of claim 4, wherein said latched host bus state comprises data, control, and address signals having particular values.

7. The computer system of claim 1, wherein said host bus cycles are pipelined, wherein an address portion is provided prior to a data portion, and said host bus has a first state at the beginning of a host bus cycle and has a second state at the end of a host bus cycle;

wherein said latching means latches said first host bus state at the beginning of said host bus cycle.

8. The computer system of claim 7, further comprising:

means coupled to said host bus and said snooping means for delaying completion of said host bus cycle until said snooping means snoops said latched host bus state if said host bus cycle is a read cycle.

9. The computer system of claim 8, wherein the computer system includes a memory controller coupled to said host bus and said random access memory for controlling accesses of said random access memory, and wherein said memory controller generates a ready signal to complete each host bus cycle;

and

wherein said delaying means provided a signal to said memory controller which prevents said memory controller from generating said ready signal.

10. The computer system of claim 8, wherein said latched host bus state comprises only address and control signals if said host bus cycle is a read cycle.

11. A computer system having guaranteed cache controller snoop access, the computer system comprising:

a host bus having a state when a cycle is executing;

random access memory coupled to said host bus;

multiple microprocessors coupled to said host bus for performing cycles on said host bus,

wherein, each of said microprocessors have an associated cache memory and cache controller coupled to said host bus for performing host bus cycles, said cache controllers including;

a snooping mechanism coupled to said host bus which snoops said host bus while other cache controllers and devices are performing cycles on said host bus which require snooping;

tag memory coupled to said snooping mechanism and said associated microprocessor which is accessed by either said associated microprocessor or said snooping mechanism at any one time;

means coupled to said host bus and said tag memory for delaying a host bus cycle if said tag memory is being accessed by said cache controller'"'"'s associated microprocessor;

means coupled to said snooping mechanism and said host bus for snooping said host bus cycle after said processor tag memory access is completed; and

means coupled to said delaying means and said snooping means for allowing said host bus cycle to complete after said snooping means completes snooping said host bus cycle.

12. The computer system of claim 11, wherein the computer system further includes a memory controller coupled to said host bus and said random access memory for controlling accesses of said random access memory, and wherein said memory controller generates a ready signal to complete each host bus cycle;

and

wherein said delaying means provides a signal to said memory controller which prevents said memory controller from generating said ready signal.