Configuration features in a configurable logic array

• US 5,336,950 A
• Filed: 02/08/1993
• Issued: 08/09/1994
• Est. Priority Date: 08/29/1991
• Status: Expired due to Term

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Pickett, Scott, Moni, Shankar, Hawley, David, Camarota, Rafael C., Popli, Sanjay
• Primary Examiner(s): Hudspeth, David R.
• Application Number:
  US08/015,415
• Time in Patent Office: 547 Days
• Field of Search: 307/465, 307/468, 307/469, 307/465.1, 365/189.08, 365/195, 364/716
• US Class Current: 326/39
• CPC Class Codes: H03K 17/223 in field-effect transistor switches
• CPC Class Codes: H03K 19/00361 in field effect transistor circuits
• CPC Class Codes: H03K 19/1736 in which the wiring can be modified
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17736 Structural details of routing resources

Abstract

The present invention is directed to various configuration features of a logic array that includes a plurality of individually configurable logic cells arranged in a matrix. These features include reconfiguration logic for reconfiguring logic cells in a selected portion of the matrix using a window-based protocol. The array also includes configuration data storage means for storing configuration data utilizable for configuring the logic elements, wherein each logic element includes a working data storage register, and reset circuitry for modifying the configuration data without modifying the working data. The array further includes read disable circuitry and write disable circuitry for disabling read access and write access, respectively, to the configuration data. The array further includes a comparison protocol mechanism for checking the configuration data against data on the array pins. The array further includes a configuration circuit for generating external addresses and that can be controlled through a data configuration file fetched from an external storage medium.

Claims

1. A configurable logic array comprising:

a plurality of individually configurable logic cells arranged in a matrix; and

reconfiguration logic connected to the matrix and operable for sequential access of multiple configurable logic cells in the matrix for reconfiguration of said multiple configurable logic cells thereby allowing for partial reconfiguration of the matrix.

2. A configurable logic array as in claim 1 and further comprising a program file for segmenting the matrix into a plurality of sets of configurable logic cells, the reconfiguration logic being operable for sequential access of configurable logic cells in a selected set of configurable logic cells.

3. A configurable logic array as in claim 2 and further comprising means connected to the reconfiguration logic for specifying one or more of the plurality of sets of configurable logic cells for reconfiguration by the reconfiguration logic.

4. A configurable logic array comprising:

a plurality of individually configurable logic elements arranged in a matrix, each configurable logic element including a storage register for storing working data;

configuration data storage protocol means for storing configuration data utilizable for configuring the configurable logic elements; and

reset circuitry connected to the configuration data storage protocol means for modifying the configuration data without modifying the working data.

5. A configurable logic array comprising:

a plurality of individually configurable logic elements arranged in a matrix;

configuration data storage protocol means for storing configuration data utilizable for configuring the configurable logic elements; and

read disable circuitry connected to the configuration data storage protocol means for disabling read access to the configuration data storage protocol means.

6. A configurable logic array comprising:

a plurality of individually configurable logic cells arranged in a matrix;

configuration data storage protocol means for storing configuration data utilizable for configuring the configurable logic cells; and

write disable circuitry connected to the configuration data storage protocol means for disabling write access to the configuration data storage means.

7. A configurable logic array comprising:

a plurality of individually configurable logic cells arranged in a matrix;

reconfiguration logic connected to the matrix and responsive to a configuration clock signal for configuring the configurable logic cells; and

clock selection means connected to the reconfiguration logic and that selects from first and second independent clock signals too provide the configuration clock signal.

8. A configurable logic array as in claim 7 and further comprising an internal clock generator that generates the first clock signal, the first clock signal having a fixed rate.

9. A configurable logic array as in claim 8 wherein the second clock signal is generated by an external clock generator, the second clock signal having a variable rate.

10. A configurable logic array comprising a plurality of individually configurable logic cells arranged in a matrix, configuration data storage protocol means for storing configuration data utilizable for configuring the logic cells, input protocol means for transferring the configuration data from an external source to the configuration data storage means, comparison protocol means for comparing the configuration data at the input protocol means with the configuration data stored in the configuration data storage means, and flag means responsive to a mismatch between identified by the comparison protocol means for generating an error flag.