On-wafer integrated circuit electrical testing

• US 5,336,992 A
• Filed: 06/03/1992
• Issued: 08/09/1994
• Est. Priority Date: 06/03/1992
• Status: Expired due to Fees

• Current Assignee: TRW Limited (Zeppelin - Stiftung der Stadt Friedrichshafen)
• Original Assignee: TRW Limited (Zeppelin - Stiftung der Stadt Friedrichshafen)
• Inventors: Chan, Steven S., Saito, Yoshio, Lau, James C., Malmgren, Richard P.
• Primary Examiner(s): NGUYEN, VINH P
• Application Number:
  US07/892,908
• Time in Patent Office: 797 Days
• Field of Search: 324/158 P, 324/158 F, 324/725, 324/158 R, 439/482
• US Class Current: 324/754.16
• CPC Class Codes: G01R 1/07357 with flexible bodies, e.g. buckling beams

Abstract

An electrical testing device is provided for testing integrated circuits located on a wafer. The testing device employs a multi-layer test circuit having a plurality of contacts for contacting the integrated circuits on a wafer. The layers of the test circuit are embedded in a flexible, supportive dielectric material which allows vertical flexing of the contacts. Cross bar switches are further employed to switch among the plurality of contacts thereby enabling the testing of individual dies of the water to be tested. A microprocessor is further included for controlling the switching and the testing of each die. In an alternate embodiment, the plurality of contacts are mechanically moved relative to the wafer to allow testing of the dies without the need for the switches.

Claims

1. An electrical testing device for testing integrated circuits on a wafer, said device comprising:

circuit means including a multilayer thin film test circuit fabricated in a flexible dielectric material, said test circuit having a plurality of conductive contacts extending therefrom for contacting contact points on circuitry on the wafer to be tested;

a dimensionally stable support material having a coefficient of thermal expansion substantially matching a coefficient of thermal expansion of said wafer located on top of said circuit means and directly above said contacts;

actuation means for forcibly contacting said support material so as to cause said conductive contacts to contact the contact points of the integrated circuit on said wafer; and

said circuit means having a plurality of conductive traces embedded within said flexible dielectric material, each of said traces being isolated therebetween and having said contacts connected thereto.

2. The device as defined in claim 1 wherein said test circuit comprises:

a first circuit layer having a first plurality of conductive traces embedded within a first layer of said flexible dielectric material and isolated therebetween, each of said first plurality of conductive traces having a first plurality of contacts extending outward therefrom; and

a second circuit layer located on top of said first circuit layer and having a second plurality of conductive traces embedded within a second layer of said flexible dielectric material, each of said second plurality of conductive traces having a second plurality of contacts extending outward therefrom.

3. The device as defined in claim 2 wherein said test circuit further comprises:

a third layer of dielectric material being located on top of said second circuit layer for providing isolation thereon.

4. The device as defined in claim 3 wherein said dielectric material of said test circuit includes a flexible material that allows the conductive traces and said contacts thereon to flex vertically, thereby providing adequate contact between each contact and said wafer to be tested.

5. The device as defined in claim 4 wherein said flexible dielectric material comprises polyimide.

6. The device as defined in claim 4 wherein said flexible dielectric material comprises benzocyclobutene.

7. The device as defined in claim 1 comprising:

processor means including a programmable microprocessor for processing the testing of said integrated circuits.

8. The device as defined in claim 7 wherein said circuit means further comprises:

a plurality of said test circuits, each of said test circuits being adapted to test a die on said wafer.

9. The device as defined in claim 8 further comprises:

a plurality of cross bar switches connected to said plurality of test circuits, said switches being activated to select one of said plurality of said test circuits one at a time.

10. The device as defined in claim 1 wherein said actuation means includes:

an air chamber for receiving pressurized air, said air chamber being located above said test circuit and having a thin flexible foil bottom portion which expands when receiving increased air pressure and provides uniform pressure to said test circuit to cause said contacts to contact the wafer to be tested.

11. The device as defined in claim 10 wherein said actuation means further includes an adjustable pressure control for controlling the pressure of the air in said air chamber.

12. The device as defined in claim 11 further comprising top and bottom fixtures for enclosing said device, said bottom fixture being adapted to maintain the wafer to be tested in a steady position during testing.

13. An electrical testing device for testing the integrated circuits on a wafer, said device comprising:

circuit means including a thin multilayer test circuit formed in a flexible dielectric material;

said circuit means having a first plurality of conductive traces embedded in a first layer of said flexible dielectric material and isolated therebetween and having a first plurality of electrical contacts extending outward therefrom,

said circuit means having a second plurality of conductive traces embedded in a second layer of said flexible dielectric material and isolated therebetween and having a second plurality of electrical contacts extending outward therefrom;

a support material having a coefficient of thermal expansion substantially matching a coefficient of thermal expansion of said wafer located on top of said circuit means and directly above said contacts for providing dimensional stability to said circuit; and

actuation means located on top of said support material for forcibly contacting said support material so as to cause said first and second plurality of electrical contacts to contact points of the integrated circuit on a wafer to be tested.

14. The device as defined in claim 13 comprising:

processor means including a programmable microprocessor for processing the testing of said integrated circuits.

15. The device as defined in claim 14 wherein said circuit means further comprises:

a plurality of said test circuits, each of said test circuits being adapted to test a die on said wafer.

16. The device as defined in claim 15 further comprises:

a plurality of cross bar switches connected to said plurality of test circuits, said switches being activated to select one of said plurality of said test circuits.

17. A method for testing electrical integrated circuits on a wafer, said method comprising:

providing a multi-layer test circuit having conductive traces embedded within a flexible dielectric material and a plurality of thin contacts extending therefrom;

applying a substantially uniform pressure to a dimensionally stable support material having a coefficient of thermal expansion substantially matching a coefficient of thermal expansion of said wafer, wherein said dimensionally stable support material is located on top of said circuit to cause said contacts to contact the electrical contacts of the integrated circuits on the wafer to be tested;

testing one die of said wafer; and

switching to another die after the testing on the previous die is completed.

18. The method as defined in claim 17 wherein the step of switching comprises selectively electrically switching said test circuit so as to switch from one die to another die.