Signal processing circuits with digital programmability

• US 5,337,230 A
• Filed: 04/30/1992
• Issued: 08/09/1994
• Est. Priority Date: 04/30/1992
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Baumgartner, Richard A., Herleikson, Earl C.
• Primary Examiner(s): RUGGIERO, JOSEPH F
• Application Number:
  US07/876,841
• Time in Patent Office: 831 Days
• Field of Search: 364/138, 364/139, 364/140, 364/131-134, 364/413.05, 364/413.06, 364/413.02, 364/DIG. 1, 364/DIG. 2, 340/825.03, 340/825.06, 340/825.07, 395/275, 395/325, 128/696, 128/700, 128/702-705, 128/708, 128/709
• US Class Current: 700/9
• CPC Class Codes: A61B 5/276 Protection against electrode failure
• CPC Class Codes: A61B 5/30 Input circuits therefor
• CPC Class Codes: A61B 5/7203 for noise prevention, reduction or removal
• CPC Class Codes: A61B 5/7242 using integration
• CPC Class Codes: G16H 40/40 for the management of medical equipment or devices, e.g. scheduling maintenance or upgrades
• CPC Class Codes: G16H 40/63 for local operation
• CPC Class Codes: H03K 5/2481 with at least one differential stage
• CPC Class Codes: H03K 5/249 using clock signals

Abstract

A mixed analog and digital integrated circuit with features which are especially useful for application as a front end for physiological signal instrumentation such as electrocardiographs, electromyographs, and electroencephalographs. The integrated circuit has 5 signal channels, each with analog amplification and analog to digital conversion. The channels can be configured for various combinations of input signal amplification, input signal summation, analog output driving, and AC impedance measurement. The integrated circuit has 2 digital serial input lines and 2 digital serial output lines, all designed for direct connection to optical couplers. Channel configuration, gain, and other parameters are externally controllable by a serial digital input signal. Up to 6 compatible devices can be serially connected in a chain.

Claims

1. An integrated circuit comprising:

a plurality of analog signal processing channels, each said signal processing channel having a plurality of digitally controllable functions; and

digital control means for controlling said plurality of digitally controllable functions, said digital control means further comprising;

a digital input signal, said digital input signal further comprising command input bits and data input bits; and

command decoder means for decoding said command input bits into a plurality of register selection signals; and

a plurality of control register means for storing said data input bits, each said control register means having a plurality of control outputs, each said control output having a plurality of control bits;

wherein each said control register means is selected by one said register selection signal within said plurality of register selection signals; and

wherein a particular control register means stores said data input bits if selected by the corresponding register selection signal; and

wherein each said digitally controllable function is controlled by one particular control output within said plurality of control outputs of one particular control register within said plurality of control registers.

2. An integrated circuit as in claim 1 wherein each said signal processing channel further comprises:

analog amplifier means for amplifying an analog input signal and generating an amplified signal; and

wherein each said analog amplifier means has a digitally controllable gain; and

wherein each said digitally controllable gain is controlled by one control output within said plurality of control outputs of one control register within said plurality of control registers.

3. An integrated circuit as in claim 2 further comprising:

averaging amplifier means for generating an external averaging output which is an amplified sum of a plurality of analog averaging inputs,

wherein there is a one-to-one correspondence between said analog averaging inputs and said amplified signals; and

,

a plurality of summation input switches,

each summation switch switchably connecting one said analog summation input to one corresponding amplified signal; and

wherein each summation switch is controlled by one particular control output within said plurality of control outputs of one particular control register within said plurality of control registers.

4. An integrated circuit as in claim 3 wherein each said signal processing channel further comprises:

input lead switching means for switching an input lead to one of the following;

an input of said analog amplifier means;

or

an output of an external amplifier, said external amplifier having an input connected to said external averaging output; and

wherein each said lead switching means is controlled by one control output within said plurality of control outputs of one control register within said plurality of control registers.

5. An integrated circuit as in claim 4 wherein each said analog signal processing channel further comprises:

analog to digital converter means for converting said amplified signal to a digital output signal;

wherein said analog to digital converter means further comprises;

clock divider means for adjusting a sample rate of said analog to digital converter means;

wherein said clock divider means is controlled by one control output within said plurality of control outputs of one control register within said plurality of control registers.

6. An integrated circuit as in claim 5 wherein each analog to digital converter means further comprises:

offset means for generating an analog offset voltage which is subtracted from said amplified signal, wherein said analog offset voltage is the output of a digital to analog converter having a digital input, wherein said digital input is connected to a digital counter output;

wherein said digital counter is incremented if said digital output is greater than a digital upper threshold for a controllable time; and

wherein said digital counter is decremented in said digital output is less than a digital lower threshold for said controllable time; and

wherein said digital upper threshold, said digital lower threshold and said controllable time are each controlled by one control output within said plurality of control outputs of one control register within said plurality of control registers.

7. An integrated circuit as in claim 6 wherein one said analog signal processing channel is an impedance measuring channel further comprising:

impedance measurement means for generating an alternating current output through an external impedance and for rectifying a resulting voltage thereby generating an impedance signal; and

impedance switching means for determining whether said impedance measuring means or said amplified signal is connected to the analog to digital converter in said impedance measuring channel; and

wherein said impedance switching means is controlled by one control output within said plurality of control outputs of one control register within said plurality of control registers.

8. An integrated circuit as in claim 2 wherein each said analog signal processing channel further comprises:

analog to digital converter means for converting said amplified signal to a digital output signal;

wherein said analog to digital converter means further comprises;

clock divider means for adjusting a sample rate of said analog to digital converter means;

wherein said clock divider means is controlled by one control output within said plurality of control outputs of one control register within said plurality of control registers.

9. An integrated circuit as in claim 8 wherein each analog to digital converter means further comprises:

offset means for generating an analog offset voltage which is subtracted from said amplified signal, wherein said analog offset voltage is the output of a digital to analog converter having a digital input, wherein said digital input is connected to a digital counter output;

wherein said digital counter is incremented if said digital output is greater than a digital upper threshold for a controllable time; and

wherein said digital counter is decremented in said digital output is less than a digital lower threshold for said controllable time; and

wherein said digital upper threshold, said digital lower threshold and said controllable time are each controlled by one control output within said plurality of control outputs of one control register within said plurality of control registers.

10. An integrated circuit as in claim 9 wherein one said analog signal processing channel is an impedance measuring channel further comprising:

impedance measurement means for generating an alternating current output through an external impedance and for rectifying a resulting voltage thereby generating an impedance signal; and

impedance switching means for determining whether said impedance measuring means or said amplified signal is connected to the analog to digital converter in said impedance measuring channel; and

wherein said impedance switching means is controlled by one control output within said plurality of control outputs of one control register within said plurality of control registers.

11. An integrated circuit as in claim 1 wherein each said analog signal processing channel further comprises:

an amplified signal; and

analog to digital converter means for converting said amplified signal to a digital output signal;

wherein said analog to digital converter means further comprises;

clock divider means for adjusting a sample rate of said analog to digital converter means;

wherein said clock divider means is controlled by one control output within said plurality of control outputs of one control register within said plurality of control registers.

12. An integrated circuit as in claim 11 wherein each analog to digital converter means further comprises:

offset means for generating an analog offset voltage which is subtracted from said amplified signal, wherein said analog offset voltage is the output of a digital to analog converter having a digital input, wherein said digital input is connected to a digital counter output;

wherein said digital counter is incremented if said digital output is greater than a digital upper threshold for a controllable time; and

wherein said digital counter is decremented in said digital output is less than a digital lower threshold for said controllable time; and

wherein said digital upper threshold, said digital lower threshold and said controllable time are each controlled by one control output within said plurality of control outputs of one control register within said plurality of control registers.

13. An integrated circuit as in claim 11 wherein one said analog signal processing channel is an impedance measuring channel further comprising:

impedance measurement means for generating an alternating current output through an external impedance and for rectifying a resulting voltage thereby generating an impedance signal; and

impedance switching means for determining whether said impedance measuring means or said amplified signal is connected to the analog to digital converter in said impedance measuring channel; and

wherein said impedance switching means is controlled by one control output within said plurality of control outputs of one control register within said plurality of control registers.

14. An integrated circuit as in claim 13 wherein each analog to digital converter means further comprises:

offset means for generating an analog offset voltage which is subtracted from said amplified signal, wherein said analog offset voltage is the output of a digital to analog converter having a digital input, wherein said digital input is connected to a digital counter output;

wherein said digital counter is incremented if said digital output is greater than a digital upper threshold for a controllable time; and

wherein said digital counter is decremented in said digital output is less than a digital lower threshold for said controllable time; and

wherein said digital upper threshold, said digital lower threshold and said controllable time are each controlled by one control output within said plurality of control outputs of one control register within said plurality of control registers.

15. An integrated circuit as in claim 11 further comprising:

averaging amplifier means for generating an external averaging output which is an amplified sum of a plurality of analog averaging inputs,

wherein there is a one-to-one correspondence between said analog averaging inputs and said amplified signals; and

,

a plurality of summation input switches,

each summation switch switchably connecting one said analog summation input to one corresponding amplified signal; and

wherein each summation switch is controlled by one particular control output within said plurality of control outputs of one particular control register within said plurality of control registers.

16. An integrated circuit as in claim 15 wherein each said signal processing channel further comprises:

input lead switching means for switching an input lead to one of the following;

an input of said analog amplifier means;

or

an output of an external amplifier, said external amplifier having an input connected to said external averaging output; and

wherein each said lead switching means is controlled by one control output within said plurality of control outputs of one control register within said plurality of control registers.

17. An integrated circuit as in claim 15 wherein each analog to digital converter means further comprises:

offset means for generating an analog offset voltage which is subtracted from said amplified signal, wherein said analog offset voltage is the output of a digital to analog converter having a digital input, wherein said digital input is connected to a digital counter output;

wherein said digital counter is incremented if said digital output is greater than a digital upper threshold for a controllable time; and

wherein said digital counter is decremented in said digital output is less than a digital lower threshold for said controllable time; and

wherein said digital upper threshold, said digital lower threshold and said controllable time are each controlled by one control output within said plurality of control outputs of one control register within said plurality of control registers.

18. An integrated circuit as in claim 17 wherein each said signal processing channel further comprises:

input lead switching means for switching an input lead to one of the following;

an input of said analog amplifier means;

or

an output of an external amplifier, said external amplifier having an input connected to said external averaging output; and

wherein each said lead switching means is controlled by one control output within said plurality of control outputs of one control register within said plurality of control registers.

19. An integrated circuit as in claim 15 wherein one said analog signal processing channel is an impedance measuring channel further comprising:

impedance measurement means for generating an alternating current output through an external impedance and for rectifying a resulting voltage thereby generating an impedance signal; and

impedance switching means for determining whether said impedance measuring means or said amplified signal is connected to the analog to digital converter in said impedance measuring channel; and

wherein said impedance switching means is controlled by one control output within said plurality of control outputs of one control register within said plurality of control registers.

20. An integrated circuit as in claim 19 wherein each analog to digital converter means further comprises:

offset means for generating an analog offset voltage which is subtracted from said amplified signal, wherein said analog offset voltage is the output of a digital to analog converter having a digital input, wherein said digital input is connected to a digital counter output;

wherein said digital counter is incremented if said digital output is greater than a digital upper threshold for a controllable time; and

wherein said digital counter is decremented in said digital output is less than a digital lower threshold for said controllable time; and

wherein said digital upper threshold, said digital lower threshold and said controllable time are each controlled by one control output within said plurality of control outputs of one control register within said plurality of control registers.