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Pulse density modulation circuit (parallel to serial) comparing in a nonsequential bit order

  • US 5,337,338 A
  • Filed: 02/01/1993
  • Issued: 08/09/1994
  • Est. Priority Date: 02/01/1993
  • Status: Expired due to Fees
First Claim
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1. A pulse density modulation circuit comprising:

  • counter means for generating a series of incremental value count signals, each count signal having a most significant bit through a least significant bit; and

    comparator means for receiving a reference signal having a most significant bit through least significant bit, comparing the reference signal with the series of count signals wherein the reference signal most significant bit through least significant bit is compared in a non-sequential bit order of the count signal most significant bit through least significant bit, and providing a single bit signal.

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