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Method for fabrication of w-polycide-to-poly capacitors with high linearity

  • US 5,338,701 A
  • Filed: 11/03/1993
  • Issued: 08/16/1994
  • Est. Priority Date: 11/03/1993
  • Status: Expired due to Term
First Claim
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1. A method for forming a polycide-to-polysilicon capacitor with a low voltage coefficient and high linearity, in and on a silicon substrate, on an integrated circuit having FET devices which are separated from each other by means of field oxide regions, comprising:

  • forming a first layer of polysilicon, having a suitable doping concentration, on the surface of said substrate and said field oxide regions;

    forming a layer of silicide over said layer of polysilicon;

    ion implanting in a vertical direction into said layer of silicide to produce said low voltage coefficient and high linearity;

    forming a layer of interpoly oxide over said layer of silicide;

    densifying said layer of interpoly oxide;

    forming a second layer of polysilicon, on the surface of said layer of interpoly oxide;

    doping said second layer of polysilicon;

    patterning said second layer of polysilicon to form the top plate of said capacitor;

    removing said layer of interpoly oxide except in the area under said top plate of said capacitor, where it acts as a capacitor dielectric;

    patterning said layer of silicide and said layer of polysilicon, to form a polycide bottom plate of said capacitor;

    annealing said polycide bottom plate; and

    forming sidewalls on the sides of said polycide bottom plate.

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