Thin film transistor with three dimensional multichannel structure

• US 5,338,959 A
• Filed: 03/30/1993
• Issued: 08/16/1994
• Est. Priority Date: 03/30/1992
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Han, Jeongin, Kim, Weonkeun, Kim, Chulsoo
• Primary Examiner(s): Sikes, William L.
• Assistant Examiner(s): Abraham, Fetsum
• Application Number:
  US08/040,016
• Time in Patent Office: 504 Days
• Field of Search: 257/331, 257/365, 257/401, 257/66, 257/364
• US Class Current: 257/331
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel

Abstract

A thin film transistor gate structure with a three-dimensional multichannel structure is disclosed.

The thin film transistor gate structure according to the present invention comprises source/drain electrodes formed so as to be spaced from and opposite to each other on a substrate; semiconductive layers, comprised of a plurality of sub-semiconductive layers, each formed in a row, each end of the sub-semiconductive layers being in ohmic-contact with the source/drain electrodes; gate insulating layers surrounding each of the semiconductive layers; and gate electrodes surrounding each of the gate insulating layers.

Accordingly, the whole outerlayers of each sub-semiconductive layer surrounded by the gate electrodes serve as channel regions. As a result, the effective channel area increases, thereby improving the channel conductance and current driving ability.

Claims

1. A thin film transistor gate structure comprising:

(a) a substrate;

(b) a plurality of spaced apart semiconductive strips formed substantially parallel to one another and to said substrate, each said strip having a channel portion;

(c) a gate insulating layer surrounding a cross-sectional periphery of each said channel portion of each said semiconductive strip; and

(d) a gate electrode surrounding said gate insulating layer, a portion of said gate electrode being disposed on said substrate.

2. A thin film transistor gate structure as set forth in claim 1, wherein said gate electrode comprises upper and lower electrode portions.

3. A thin film transistor gate structure as set forth in claim 2, wherein said gate insulating layer comprises upper and lower insulating portions.

4. A thin film transistor gate structure as set forth in claim 1, wherein a cross-section of each said semiconductive strip is polygonal.

5. A thin film transistor gate structure as set forth in claim 1, wherein a cross-section of each said semiconductive strip channel portion is substantially circular.

6. A thin film transistor gate structure as set forth in claim 1, wherein a thickness of each said semiconductive strip channel portion is thicker than an effective channel thickness of the transistor.

7. The thin film transistor gate structure as set forth in claim 1, wherein the thickness of each said semiconductive strip channel portion is equal to an effective channel thickness of the transistor.

8. The thin film transistor gate structure as set forth in claim 1, wherein said semiconductive strips are formed of polycrystalline silicon.

9. The thin film transistor gate structure as set forth in claim 1, wherein said substrate is made from a material through which light can be transmitted.

10. A thin film transistor gate structure as set forth in claim 1, wherein said substrate is made from a material selected from the group consisting of glass, quartz, amorphous, silicon, or crystalline silicon.