High power MOSFET with low on-resistance and high breakdown voltage

• US 5,338,961 A
• Filed: 02/12/1993
• Issued: 08/16/1994
• Est. Priority Date: 10/13/1978
• Status: Expired due to Fees

• Current Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Lidow, Alexander, Herman, Thomas
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): LOKE, STEVEN HO YIN
• Application Number:
  US08/017,511
• Time in Patent Office: 550 Days
• Field of Search: 257/327, 257/339, 257/341, 257/342, 257/343, 257/213
• US Class Current: 257/342
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors

Abstract

A high power MOSFET is disclosed in which two laterally spaced sources each supply current through respective channels in one surface of a semiconductor chip which are controlled by the same gate. The channels lead from the source electrodes to a relatively low resistivity region and from there to a relatively high resistivity epitaxially formed region which is deposited on a high conductivity substrate. The drain electrode may be either on the opposite surface of the chip or laterally displaced from and on the same side as the source regions. The epitaxially deposited semiconductor material immediately adjacent and beneath the gate and in the path from the sources to the drain has a relatively high conductivity, thereby to substantially reduce the on-resistance of the device without effecting the breakdown voltage of the device. The breakdown voltage of the device is substantially increased by forming a relatively deep p-type diffusion with a large radius in the n-type epitaxial layer beneath each of the sources.

Claims

1. A high power metal oxide silicon field effect transistor device exhibiting relatively low on-resistance and relatively high breakdown voltage;

said device comprising;

a wafer of semiconductor material having first and second opposing semiconductor surfaces;

said wafer of semiconductor material having a relatively lightly doped major body portion for receiving junctions and being doped with impurities of one conductivity type;

at least first and second spaced base regions of the opposite conductivity type to said one conductivity type formed in said wafer and extending from said first semiconductor surface to a first depth beneath said first semiconductor surface;

the space between said at least first and second base regions defining a common conduction region of one conductivity type at a given first semiconductor surface location;

first and second source regions of said one conductivity type formed in each pair of said at least first and second base regions respectively at first and second first surface locations and extending from said first and second first surface locations to a depth less than said first depth;

said first and second source regions being laterally spaced along said first semiconductor surface from the facing respective edges of said common conduction region thereby to define first and second channel regions along said first semiconductor surface between each pair of said first and second source regions, respectively and said common conduction region;

source electrode means connected to said source regions;

gate insulation layer means on said surface, disposed at least on said first and second channel regions;

gate electrode means on said gate insulation layer means;

said gate electrode means overlying said first and second channel regions;

a drain conductive region remote from said common region and separated therefrom by said relatively lightly doped major body portion;

a drain electrode coupled to said drain conductive region;

said common region being relatively highly doped, compared to said relatively lightly doped major body portion and extending from said given first semiconductor surface location to a depth greater than the depth of said source region, whereby resistance to current flow at the junctures between said first and second surface channel regions and said common region and between said common region and said relatively lightly doped major body portion is reduced;

said first and second source regions being formed by a process step in which the impurities for defining said first and second source regions are applied to said first and second first surface locations in a single step.

2. The high power metal oxide silicon field effect transistor device of claim 1 wherein said device is formed by DMOS manufacturing techniques.

3. The high power metal oxide silicon field effect transistor device of claim 1;

said at least first and second spaced base regions being diffused regions and being diffused from said first and second first surface locations to said common regions.

4. The device of claim 1 wherein said drain electrode is on said second semiconductor surface.

5. The device of claim 1 wherein said drain electrode is on said first surface.

6. The device of claim 5 wherein said drain conductive region is a high conductivity diffused region and is disposed beneath said drain electrode.

7. The device of claim 6 which further includes electrode means fixed to said second surface.

8. The device of claim 5 wherein a buried conductive region contacts a region of said opposite conductivity type which extends from said buried conductive region to said second surface.

9. The device of claim 8 wherein there is at least one additional highly doped isolation region of said opposite conductivity type extending into said wafer from said first surface and surrounding said device.

10. The device of claim 5 further comprising a generally annular, low-resistivity region of said opposite conductivity type surrounding said drain electrode;

said generally annular region extending deep enough into said wafer to isolate said device electrically from other components on said wafer.

11. The device of claim 5, wherein said one conductivity type is N-type and said opposite conductivity type is P-type.

12. The device of claim 1 wherein said relatively lightly doped major body portion of said wafer is an epitaxially formed layer.

13. the device of claim 12 wherein said epitaxial layer has a thickness of about 20 microns and is dependent upon the desired reverse voltage of the device.

14. The device of claim 1 wherein said gate insulation layer means is silicon dioxide.

15. The device of claim 1 wherein said first and second channel regions and said gate electrode means are elongated along a closed serpentine path.

16. The device of claim 1 wherein said first and second channel regions are elongated around closed parallel paths.

17. The device of claim 16 wherein one of said first and second source regions surrounds the other.

18. The device of claim 1 wherein said one conductivity type is the n-type and wherein said opposite conductive type is the p-type.

19. The device of claim 1 wherein each of said at least first and second spaced base regions of said opposite conductivity type have respective profiles which includes relatively shallow depth regions extending from said common region and underlying their said respective first and second source regions, and respective relatively deep, relatively large radius regions extending from said shallow depth regions which are laterally spaced from beneath said respective source regions on the side of said source regions which is away from said common region.

20. The device of claim 19 wherein said relatively deep regions have a depth of about 4 microns.

21. The device of claim 1 wherein said depth to which said common region is relatively highly doped is greater than about 1 micron.

22. The device of claim 1 wherein said depth to which said common region is highly doped is about 3 to 6 microns.

23. The device of claim 1 wherein said gate electrode means is formed of polysilicon.

24. The device of claim 1 wherein said relatively lightly doped body portion has a resistivity greater than about 2.5 ohm centimeters.

25. The device of claim 1 wherein said relatively highly doped common region is doped to a conductivity which is of the order of magnitude which would be produced by a total ion implanted dose of about 1×

10¹² to 1×

10¹⁴ phosphorus atoms/cm² at 50 kv.

26. A high power metal oxide silicon field effect transistor device exhibiting relatively low on-resistance and relatively high breakdown voltage;

said device comprising;

a wafer of semiconductor material having first and second opposing semiconductor surfaces;

said wafer of semiconductor material having a relatively lightly doped major body portion for receiving junctions and being doped with impurities of one conductivity type;

at least first and second spaced base regions of the opposite conductivity type to said one conductivity type formed in said wafer and extending from said first semiconductor surface to a first depth beneath said first semiconductor surface;

the space between said at least first and second base regions defining a common conduction region of one conductivity type at a given first semiconductor surface location;

first and second source regions of said one conductivity type formed in each pair of said at least first and second base regions respectively at first and second first surface locations and extending from said first and second first surface locations to a depth less than said first depth;

said first and second source regions being laterally spaced along said first semiconductor surface from the facing respective edges of said common conduction region thereby to define first and second channel regions along said first semiconductor surface between each pair of said first and second source regions, respectively and said common conduction region;

source electrode means connected to said source regions;

gate insulation layer means on said first surface, disposed at least on said first and second channel regions;

gate electrode means on said gate insulation layer means;

said gate electrode means overlying said first and second channel regions;

a drain conductive region remote from said common region and separated therefrom by said relatively lightly doped major body portion;

a drain electrode coupled to said drain conductive region;

said common region being relatively highly doped, compared to said relatively lightly doped major body portion and extending from said given first semiconductor surface location to a depth greater than the depth of said source region but less than said first depth of said first and second spaced base regions, whereby resistance to current flow at the junctures between said first and second surface channel regions and said common region and between said common region and said relatively lightly doped major body portion is reduced;

said first and second source regions being formed by a process step in which the impurities for defining said first and second source regions are applied to said first and second first surface locations in a single step.

27. The high power metal oxide silicon field effect transistor device of claim 26 wherein said device is formed by D-MOS manufacturing techniques.

28. The high power metal oxide silicon field effect transistor device of claim 26;

said at least first and second spaced base regions being diffused regions and being diffused from said first and second first surface locations to said common region.

29. The device of claim 26 wherein said drain electrode is on said second semiconductor surface.

30. The device of claim 26 wherein said drain electrode is on said first surface.

31. The device of claim 30 wherein said drain conductive region is a high conductivity diffused region and is disposed beneath said drain electrode.

32. The device of claim 31 which further includes electrode means fixed to said second surface.

33. The device of claim 30 wherein a buried conductive region contacts a region of said opposite conductivity type which extends from said buried conductive region to said second surface.

34. The device of claim 33 wherein there is at least one additional highly doped isolation region of said opposite conductivity type extending into said wafer from said first surface and surrounding said device.

35. The device of claim 30, further comprising a generally annular, low-resistivity region of said opposite conductivity type surrounding said drain electrode;

said generally annular region extending deep enough into said wafer to isolate said device electrically from other components on said wafer.

36. The device of claim 30, wherein said one conductivity type is N-type and said opposite conductivity type is P-type.

37. The device of claim 26 wherein said relatively lightly doped major body portion of said wafer is an epitaxially formed layer.

38. The device of claim 37 wherein said epitaxial layer has a thickness of about 20 microns and is dependent upon the desired reverse voltage of the device.

39. The device of claim 26 wherein said gate insulation layer means is silicon dioxide.

40. The device of claim 26 wherein said first and second channel regions and said gate electrode means are elongated along a closed serpentine path.

41. The device of claim 26 wherein said first and second channel regions are elongated around closed parallel paths.

42. The device of claim 41 wherein one of said first and second source regions surrounds the other.

43. The device of claim 26 wherein said one conductivity type is the n-type and wherein said opposite conductivity type is the p-type.

44. The device of claim 26 wherein each of said at least first and second spaced base regions of said opposite conductivity type have respective profiles which include relatively shallow depth regions extending from said common region and underlying their said respective first and second source regions, and respective relatively deep, relatively large radius regions extending from said shallow depth regions which are laterally spaced from beneath said respective source regions on the side of said source regions which is away from said common region.

45. The device of claim 44 wherein said relatively deep regions have a depth of about 4 microns.

46. The device of claim 26 wherein said depth to which said common region is relatively highly doped is greater than about 1 micron.

47. The device of claim 26 wherein said depth to which said common region is highly doped is about 3 to 6 microns.

48. The device of claim 26 wherein said gate electrode means is formed of polysilicon.

49. The device of claim 26 wherein said relatively lightly doped body portion has a resistivity greater than about 2.5 ohm centimeters.

50. The device of claim 26 wherein said relatively highly doped common region is doped to a conductivity which is of the order of magnitude which would be produced by a total ion implanted dose of about 1×

10¹² to 1×

10¹⁴ phosphorus atoms/cm² at 50 kv.