Semiconductor device structure with plated heat sink and supporting substrate

• US 5,338,967 A
• Filed: 05/06/1993
• Issued: 08/16/1994
• Est. Priority Date: 01/12/1993
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Kosaki, Katsuya
• Primary Examiner(s): Crane, Sara W.
• Assistant Examiner(s): GUAY, JOHN FRANCIS
• Application Number:
  US08/057,790
• Time in Patent Office: 467 Days
• Field of Search: 257/703, 257/706, 257/712, 257/720, 257/705, 257/713, 257/620, 257/707, 437/226, 437/227
• US Class Current: 257/620
• CPC Class Codes: H01L 2224/29111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/29144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/83191 wherein the layer connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83801 Soldering or alloying
• CPC Class Codes: H01L 23/3735 Laminates or multilayers, e.g. direct bond copper ceramic substrates
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/27 Manufacturing methods
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01028 Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01042 Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01045 Rhodium [Rh]
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/0133 : Ternary Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1423 : Monolithic Microwave Integrated Circuit [MMIC]
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/3511 : Warping
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

A semiconductor chip includes a semiconductor substrate having opposite front and rear surfaces and an active element on the front surface and a supporting substrate supporting the semiconductor substrate and disposed on the rear surface of the semiconductor substrate. The supporting substrate includes a radiating layer for radiating heat generated by the active element and disposed on a part of the rear surface of the semiconductor substrate directly opposite said active element and a plated metal layer of Rh, Pt, or Ni-B-W having a linear thermal expansion coefficient approximately equal to that of the semiconductor substrate and disposed on part of the rear surface of the semiconductor substrate but not directly opposite the active element. In this structure, the curvature of the chip during die-bonding is reduced. The plated metal layer is produced in a relatively simple process with no difficulty in controlling the composition of a plating solution. As a result, a semiconductor chip having improved heat radiation and RF characteristics is achieved.

Claims

1. A semiconductor device structure comprising:

a semiconductor substrate having opposite front and rear surfaces and an active element on the front surface; and

a supporting substrate supporting said semiconductor substrate and disposed on the rear surface of the semiconductor substrate, said supporting substrate comprising;

a radiating layer for radiating heat generated by said active element and disposed on a part of the rear surface of said semiconductor substrate directly opposite said active element, and p2 a plated metal layer selected from the group consisting of Rh, Pt, and Ni-B-W, said plated metal layer having a linear thermal expansion coefficient nearer to the linear thermal expansion coefficient of said semiconductor substrate than the linear thermal expansion coefficient of said radiating layer and disposed on part of the rear surface of said semiconductor substrate but not directly opposite said active element.

2. The semiconductor device structure of claim 1 wherein said semiconductor substrate includes dicing lines extending into said substrate at the front surface and said supporting substrate includes plated hard metal layers comprising a metal harder than other portions of said supporting substrate disposed on part of the rear surface of said semiconductor substrate directly opposite the dicing lines.

3. The semiconductor device structure of claim 2 wherein said plated hard metal layers are selected from the group consisting of Ni, Ni-P, and Au-Sn alloy.

4. The semiconductor device structure of claim 2 comprising a second metal layer disposed in the dicing lines.

5. A semiconductor device structure comprising;

a semiconductor substrate having opposite front and rear surfaces, dicing lines extending into said substrate at the front surface, and an active element on the front surface; and

a supporting substrate supporting said semiconductor substrate and disposed on the rear surface of the semiconductor substrate, said supporting substrate comprising;

a metal harder than other portions of said supporting substrate disposed on part of the rear surface of said semiconductor substrate directly opposite the dicing lines;

a radiating layer for radiating heat generated by said active element and disposed on a part of the rear surface of said semiconductor substrate directly opposite said active element, and

a ceramic layer having a linear thermal expansion coefficient nearer to the linear thermal expansion coefficient of said semiconductor substrate than the linear thermal expansion coefficient of said radiating layer and disposed on part of the rear surface of said semiconductor substrate but not directly opposite said active element.

6. The semiconductor device structure of claim 5 wherein said metal is selected from the group consisting of Ni, Ni-P, and Au-Sn alloy.

7. A semiconductor device structure comprising:

a semiconductor substrate having opposite front and rear surfaces and an active element on the front surface; and

a supporting substrate supporting said semiconductor substrate and disposed on the rear surface of the semiconductor substrate, said supporting substrate comprising;

a radiating layer for radiating heat generated by said active element and disposed on a part of the rear surface of said semiconductor substrate directly opposite said active element, and

a plated metal layer comprising, alternatingly laminated, Au and one selected from the group consisting of Rh, Pt, and Ni-B-W, said plated metal layer having a linear thermal expansion coefficient nearer to the linear thermal expansion coefficient of said semiconductor substrate than the linear thermal expansion coefficient of said radiating layer and disposed on part of the rear surface of said semiconductor substrate but not directly opposite said active element.

8. The semiconductor device structure of claim 7 wherein said semiconductor substrate includes dicing lines extending into said substrate at the front surface and said supporting substrate includes plated hard metal layers comprising a metal harder than other portions of said supporting substrate disposed on part of the rear surface of said semiconductor substrate directly opposite the dicing lines.

9. The semiconductor device structure of claim 8 wherein said plated hard metal layers are selected from the group consisting of Ni, Ni-P, and Au-Sn alloy.

10. The semiconductor device structure of claim 8 comprising a second metal layer disposed in the dicing lines.