Latch-up resistant CMOS output circuit

• US 5,338,986 A
• Filed: 05/18/1993
• Issued: 08/16/1994
• Est. Priority Date: 05/28/1992
• Status: Expired due to Term

• Current Assignee: Oki Semiconductor Company Limited (ROHM Co., Ltd.)
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Kurimoto, Masahiro
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): LE, DINH THANH
• Application Number:
  US08/062,754
• Time in Patent Office: 455 Days
• Field of Search: 257/372, 257/386, 257/401, 257/409, 257/340, 257/774, 257/775, 257/379, 257/380, 257/373, 307/303, 307/303.1, 307/303.2
• US Class Current: 327/566
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/0921 Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention

Abstract

A CMOS output circuit including a pMOS transistor and an nMOS transistor connected in series between a power supply voltage and a ground voltage, is formed with a resistive component for reducing occurrence of latch-up. The resistive component is arranged at least one of the sources of the pMOS and nMOS transistors so as to be connected in series with a parasitic bipolar transistor formed between the power supply voltage and the ground voltage through its emitter. The resistive component limits the collector current of the parasitic bipolar transistor at a time that a triggering voltage is applied to an output terminal of the output circuit, so that the parasitic bipolar transistor does not turn on readily, thereby resulting in reduced possibility of occurrence of latch-up.

Claims

1. A CMOS output circuit for outputting a signal to an output terminal thereof, activated by supplying a higher voltage and a lower voltage, comprising:

a substrate of a first conductivity, having a major surface and being fed with one of said higher and lower voltages;

a well of a second conductivity opposite to said first conductivity, having a major surface, being formed in said substrate, and being fed with the other of said higher and lower voltages;

a first MOS transistor, being formed on said major surface of said well, and having a source of said first conductivity being fed with said other of said higher and lower voltages, and a drain of said first conductivity being connected to said output terminal;

a second MOS transistor being formed on said major surface of said substrate, and having a source of said first conductivity being fed with said one of said higher and lower voltages, and a drain of said first conductivity being connected to said output terminal; and

a resistive component provided at least at one of the sources of said first and second MOS transistors so as to be serially connected to a parasitic bipolar transistor whose emitter is formed by said one of the sources, wherein said resistive component is formed from a layout in which a distance between a contact for said source of one of said first and second MOS transistors and a gate of said one of said first and second MOS transistors is longer than a distance between a contact for said drain of said one of said first and second MOS transistors and said gate of said one of said first and second MOS transistors.

2. A CMOS output circuit as set forth in claim 1, wherein said first conductivity is n-type;

said second conductivity is p-type;

said one of said higher and lower voltages is said higher voltage; and

said other of said higher and lower voltages is said lower voltage.

3. A CMOS output circuit as set forth in claim 1, wherein said first conductivity is p-type;

said second conductivity is n-type;

said one of said higher and lower voltages is said lower voltage; and

said other of said higher and lower voltages is said higher voltage.

4. A CMOS output circuit as set forth in claim 1, wherein said resistive component is provided at both of said sources.

5. A CMOS output circuit for outputting a signal to an output terminal thereof, activated by supplying a higher voltage and a lower voltage, comprising:

a substrate of a first conductivity, having a major surface and being fed with one of said higher and lower voltages;

a well of a second conductivity opposite to said first conductivity, having a major surface, being formed in said substrate, and being fed with the other of said higher and lower voltages;

a first MOS transistor, being formed on said major surface of said well, and having a source of said first conductivity being fed with said other of said higher and lower voltages, and a drain of said first conductivity being connected to said output terminal;

a second MOS transistor being formed on said major surface of said substrate, and having a source of said first conductivity being fed with said one of said higher and lower voltages, and a drain of said first conductivity being connected to said output terminal; and

a resistive component provided at least at one of the sources of said first and second MOS transistors so as to be serially connected to a parasitic bipolar transistor whose emitter is formed by said one of the sources, wherein said resistive component is formed from a layout of the circuit in which the number of contacts for said source of one of said first and second MOS transistors is less than the number of contacts for said drain of said one of said first and second MOS transistors.

8. A CMOS output circuit as set forth in claim 5, wherein said first conductivity is n-type;

said second conductivity is p-type;

said one of said higher and lower voltages is said higher voltage; and

said other of said higher and lower voltages is said lower voltage.

9. A CMOS output circuit as set forth in claim 5, wherein said first conductivity is p-type;

said second conductivity is n-type;

said one of said higher and lower voltages is said lower voltage; and

said other of said higher and lower voltages is said higher voltage.

10. A CMOS output circuit as set forth in claim 5, wherein said resistive component is provided at both of said sources.

6. A CMOS output circuit for outputting a signal to an output terminal thereof, activated by supplying a higher voltage and a lower voltage, comprising:

a substrate of a first conductivity, having a major surface and being fed with one of said higher and lower voltages;

a well of a second conductivity opposite to said first conductivity, having a major surface, being formed in said substrate, and being fed with the other of said higher and lower voltages;

a first MOS transistor, being formed on said major surface of said well, and having a source of said first conductivity being fed with said other of said higher and lower voltages, and a drain of said first conductivity being connected to said output terminal;

a second MOS transistor being formed on said major surface of said substrate, and having a source of said first conductivity being fed with said one of said higher and lower voltages, and a drain of said first conductivity being connected to said output terminal; and

a resistive component formed from a layout in which a distance between a contact for said source of one of said first and second MOS transistors and a gate of said one of said first and second MOS transistors is longer than a distance between a contact for said drain of said one of said first and second MOS transistors and said gate of said one of said first and second MOS transistors.

7. A CMOS output circuit for outputting a signal to an output terminal thereof, activated by supplying a higher voltage and a lower voltage, comprising:

a substrate of a first conductivity, having a major surface and being fed with one of said higher and lower voltages;

a well of a second conductivity opposite to said first conductivity, having a major surface, being formed in said substrate, and being fed with the other of said higher and lower voltages;

a first MOS transistor, being formed on said major surface of said well, and having a source of said first conductivity being fed with said other of said higher and lower voltages, and a drain of said first conductivity being connected to said output terminal;

a second MOS transistor being formed on said major surface of said substrate, and having a source of said first conductivity being fed with said one of said higher and lower voltages, and a drain of said first conductivity being connected to said output terminal; and

a resistive component formed from a layout in which the number of contacts for said source of one of said first and second MOS transistors is less than the number of contacts for said drain of said one of said first and second MOS transistors.

11. A CMOS output circuit for outputting a signal, activated by supplying a higher voltage and a lower voltage, comprising:

a substrate of a first conductivity, having a major surface and being fed with one of the higher and lower voltages;

a well of a second conductivity opposite to the first conductivity, having a major surface, being formed in said substrate, and being fed with the other of the higher and lower voltages;

a first MOS transistor formed on said major surface of said well, said first MOS transistor having a source of the first conductivity fed with the other of the higher and lower voltages, a drain of the first conductivity, and a gate;

a second MOS transistor formed on said major surface of said substrate, said second MOS transistor having a source of the first conductivity fed with the one of the higher and lower voltages, a drain of the first conductivity, and a gate;

a power supply electrode disposed on the source of one of said first and second MOS transistors;

an output terminal for receiving the output signal, said output terminal disposed on said drain of said one of said first and second MOS transistors; and

an arrangement of contacts connecting said power supply electrode to the source of said one of said first and second MOS transistors on one side of the gate of said one of said first and second MOS transistors, and connecting said output terminal to the drain of said one of said first and second MOS transistors on a side of said gate opposite said one side, said arrangement being asymmetrical with respect to said gate of said one of said first and second MOS transistors, the asymmetry providing a parasitic resistance at said source of said one of said first and second MOS transistors, the parasitic resistance serially connected to a parasitic bipolar transistor whose emitter is formed by said source of said one of said first and second MOS transistors.

12. A CMOS output circuit as set forth in claim 11, wherein said contacts include at least one first contact on said one side of said gate of said one of said first and second CMOS transistors, and at least one second contact on the opposite side of said gate of said one of said first and second MOS transistors, and wherein the asymmetry is in distance of the at least one first contact and the at least one second contact from said gate of said one of said first and second MOS transistors, a distance of said at least one first contact from said gate of said one of said first and second MOS transistors being greater than a distance of said at least one second contact from said gate of said one of said first and second MOS transistors.

13. A CMOS output circuit as set forth in claim 11, wherein said contacts include a plurality of first contacts on one side of said gate of said one of said first and second MOS transistors, and a plurality of second contacts on the opposite side of said gate of said one of said first and second MOS transistors, and wherein the asymmetry is in the respective numbers of the first and second contacts, the number of first contacts being less than the number of second contacts.