DMD architecture and timing for use in a pulse-width modulated display system

• US 5,339,116 A
• Filed: 10/15/1993
• Issued: 08/16/1994
• Est. Priority Date: 04/01/1991
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Sampsell, Jeffrey B., Urbanus, Paul M.
• Primary Examiner(s): Powell, Mark R.
• Application Number:
  US08/137,650
• Time in Patent Office: 305 Days
• Field of Search: 358/160, 358/233, 365/230.1, 365/230.3, 365/230.6, 345/200, 345/108, 345/203
• US Class Current: 348/716
• CPC Class Codes: G09G 2310/0205 Simultaneous scanning of several lines in flat panels
• CPC Class Codes: G09G 2310/061 for resetting or blanking
• CPC Class Codes: G09G 2352/00 Parallel handling of streams of display data
• CPC Class Codes: G09G 2360/18 Use of a frame buffer in a display terminal, inclusive of the display panel
• CPC Class Codes: G09G 3/2018 by time modulation using two or more time intervals
• CPC Class Codes: G09G 3/2022 using sub-frames
• CPC Class Codes: G09G 3/2037 with specific control of sub-frames corresponding to the least significant bits
• CPC Class Codes: G09G 3/2092 Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165
• CPC Class Codes: G09G 3/346 based on modulation of the reflection angle, e.g. micromirrors micromirrors devices per se G02B26/0833
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory
• CPC Class Codes: G09G 5/395 Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen G09G5/399 takes precedence
• CPC Class Codes: G09G 5/399 using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers
• CPC Class Codes: H04N 2005/7466 Control circuits therefor
• CPC Class Codes: H04N 3/08 having a moving reflector
• CPC Class Codes: H04N 3/127 using liquid crystals
• CPC Class Codes: H04N 5/7458 the modulator being an array of deformable mirrors, e.g. digital micromirror device [DMD]
• CPC Class Codes: H04N 9/30 using solid-state colour display devices

Abstract

It is possible to replace a standard tuning unit in a television with spatial light modulator circuitry to improve the resolution seen by the viewer. The invention herein provides a system architecture, individual part of the system and techniques for minimizing the burst data rate while maintaining a reasonable system speed. The resultant system provides better resolution with a manageable data rate and bandwidth.

Claims

1. A method of displaying data comprising address memory cells and loading display data into said memory cells, wherein said display data is comprised of at least two data bits, transferring the contents of said memory cells onto display pixels so that each said data bit is displayed for a portion of the total frame time appropriate for the level of significance of said data bit.

2. The method of claim 1 wherein said display pixels are grouped into blocks, further comprising clearing at least one of said blocks of said display pixels while displaying data with another of said blocks.

3. The method of claim 1 wherein said display pixels are grouped into 8 blocks.

4. The method of claim 1 wherein said display pixels are grouped into blocks, such that one block is loaded during a period equal to the shortest data bit display period.

5. The method of claim 1 wherein all said data bits of an equivalent significance are not displayed simultaneously.

6. The method of claim 1 wherein all data bits of an equivalent significance are displayed simultaneously, said method further comprising loading said data bits for a subsequent display period during a present display period when said present display period is longer than the time required to load said data bits for said subsequent display period.

7. The method of claim 1 wherein all data bits of an equivalent significance are displayed simultaneously, said method further comprising clearing all of said display pixels after all display periods which are shorter than the time required to load data bits for a subsequent display period, and loading said data bits for a subsequent period while said display pixels are cleared.

8. The method of claim 1 wherein not all of said at least two bits are displayed in order of said significance.

9. The method of claim 1 wherein the display period for at least one of said data bits is comprised of at least two non-contiguous sub-periods.

10. A method of displaying data comprising:

a. providing a display data word, said data word having at least two data bits;

b. loading one of said data bits into a memory cell;

c. displaying said data bit by altering the state of a display pixel based on said data bit loaded in said memory cell, wherein said display pixel is altered for a display period dependent on the level of significance of said data bit loaded in said memory cell;

d. loading another one of said data bits into a memory cell during said display period;

e. repeating said steps of displaying said data bit and loading another one of said data bits until all of said at least two data bits have been displayed.

11. The method of claim 10 wherein said display pixels are grouped into blocks, further comprising clearing at least one said blocks of said display pixels while displaying data with another of said blocks.

12. The method of claim 10 wherein said display pixels are grouped into 8 blocks.

13. The method of claim 10 wherein said display pixels are grouped into blocks, such that one block is loaded during a period equal to the shortest data bit display period.

14. The method of claim 10 wherein all said data bits of an equivalent significance are not displayed simultaneously.

15. The method of claim 10 wherein the display period for at least one of said data bits is comprised of at least two non-contiguous sub-periods.

16. A method of displaying data comprising:

a. providing a display data word, said data word having at least two data bits;

b. loading one of said data bits into a memory cell;

c. displaying said data bit by altering the state of a display pixel based on said data bit loaded in said memory cell, wherein said display pixel is altered for a display period dependent on the level of significance of said data bit loaded in said memory cell;

d. clearing said display pixel at the end of said display period;

e. loading another one of said data bits into a memory cell;

f. repeating said steps of displaying said data bit, clearing said display, pixel, and loading another one of said data bits until all of said at least two data bits have been displayed.

17. The method of claim 16 wherein said display pixels are grouped into blocks, further comprising clearing at least one of said blocks of said display pixels while displaying data with another of said blocks.

18. The method of claim 16 wherein said display pixels are grouped into blocks, such that one block is loaded during a period equal to the shortest data bit display period.

19. The method of claim 16 wherein all said data bits of an equivalent significance are not displayed simultaneously.

20. The method of claim 16 wherein the display period for at least one of said data bits is comprised of at least two non-contiguous sub-periods.