Analog memory system

• US 5,339,275 A
• Filed: 03/16/1990
• Issued: 08/16/1994
• Est. Priority Date: 12/28/1970
• Status: Expired due to Term

• Current Assignee: Gilbert P. Hyatt
• Original Assignee: Gilbert P. Hyatt
• Inventors: Hyatt, Gilbert P.
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US07/495,808
• Time in Patent Office: 1,614 Days
• Field of Search: 365/45, 365/183, 365/222, 365/230.06
• US Class Current: 365/45
• CPC Class Codes: B60R 16/0373 Voice control in general G10L
• CPC Class Codes: F21V 23/00 Arrangement of electric circuit elements in or on lighting devices characterised by cooling arrangements F21V29/508
• CPC Class Codes: G01S 15/897 using application of holographic techniques
• CPC Class Codes: G01S 15/8977 using special techniques for image reconstruction, e.g. FFT, geometrical transformations, spatial deconvolution, time deconvolution
• CPC Class Codes: G01S 7/52026 Extracting wanted echo signals Doppler systems G01S15/50; Doppler short range imaging systems G01S15/8979
• CPC Class Codes: G02F 1/13318 Circuits comprising a photodetector
• CPC Class Codes: G03F 9/7049 Technique, e.g. interferometric
• CPC Class Codes: G03F 9/7088 Alignment mark detection, e.g. TTR, TTL, off-axis detection, array detector, video detection
• CPC Class Codes: G04G 99/006 Electronic time-pieces using a microcomputer, e.g. for multi-function clocks
• CPC Class Codes: G05B 19/351 the positional error is used to control continuously the servomotor according to its magnitude
• CPC Class Codes: G05B 19/408 characterised by data handling or data format, e.g. reading, buffering or conversion of data
• CPC Class Codes: G05B 19/4083 Adapting programme, configuration
• CPC Class Codes: G05B 19/4086 Coordinate conversions; Other special calculations
• CPC Class Codes: G05B 19/409 characterised by using manual data input [MDI] or by using control panel, e.g. controlling functions with the panel; characterised by control panel details or by setting parameters G05B19/408, G05B19/4093 take precedence
• CPC Class Codes: G05B 19/4093 characterised by part programming, e.g. entry of geometrical information as taken from a technical drawing, combining this with machining and material information to obtain control information, named part programme, for the NC machine
• CPC Class Codes: G05B 19/414 Structure of the control system, e.g. common controller or multiprocessor systems, interface to servo, programmable interface controller
• CPC Class Codes: G05B 19/4142 characterised by the use of a microprocessor G05B19/4141 takes precedence
• CPC Class Codes: G05B 2219/33182 Uart, serial datatransmission, modem
• CPC Class Codes: G05B 2219/34023 Risc processor
• CPC Class Codes: G05B 2219/34098 Slope fitting, fairing contour, curve fitting, transition
• CPC Class Codes: G05B 2219/34471 : Program memory is inhibited, not accessible as long as power fails
• CPC Class Codes: G05B 2219/34472 : Configure alterable memory as read only, to avoid erasing
• CPC Class Codes: G05B 2219/35262 : Macro instruction, canned cycles, subroutines, subprogram
• CPC Class Codes: G05B 2219/35263 : Using variables, parameters in program, macro, parametrized instruction
• CPC Class Codes: G05B 2219/35373 : Data storage, buffer
• CPC Class Codes: G05B 2219/35431 : Interactive
• CPC Class Codes: G05B 2219/35436 : Means, manual input, input reference, hand wheel
• CPC Class Codes: G05B 2219/35453 : Voice announcement, oral, speech input
• CPC Class Codes: G05B 2219/35472 : Mode selection
• CPC Class Codes: G05B 2219/35554 : Mirror, other conversions
• CPC Class Codes: G05B 2219/36152 : Panel
• CPC Class Codes: G05B 2219/36333 : Selection from standard forms, shapes, partprograms, enter value for variable
• CPC Class Codes: G05B 2219/36366 : Data, read in, distribution
• CPC Class Codes: G05B 2219/36379 : Read in
• CPC Class Codes: G05B 2219/36503 : Adapt program to real coordinates, software orientation
• CPC Class Codes: G05B 2219/36546 : Memory protection, protected fields
• CPC Class Codes: G05B 2219/41021 : Variable gain
• CPC Class Codes: G05B 2219/42237 : Pwm pulse width modulation, pulse to position modulation ppm
• CPC Class Codes: G05B 2219/45214 : Gear cutting
• CPC Class Codes: G05B 2219/45215 : Thread cutting
• CPC Class Codes: G05B 2219/49221 : Control of scale
• CPC Class Codes: G05B 2219/50047 : Positioning, indexing
• CPC Class Codes: G05B 2219/50048 : Jogging
• CPC Class Codes: G05B 2219/50083 : Power loss, measures again loss of power
• CPC Class Codes: G05B 2219/50151 : Orient, translate, align workpiece to fit position assumed in program
• CPC Class Codes: G06F 13/16 : for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06J 1/00 : Hybrid computing arrangements digitally-programmed analogue computers G06G7/06
• CPC Class Codes: G07G 1/12 : electronically operated digital data processing aspects G06Q20/00
• CPC Class Codes: G10L 19/00 : Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis in musical instruments G10H
• CPC Class Codes: G11C 11/565 : using capacitive charge storage elements
• CPC Class Codes: G11C 16/3418 : Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3431 : Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 19/287 : Organisation of a multiplicity of shift registers
• CPC Class Codes: G11C 19/36 : using multistable semiconductor elements
• CPC Class Codes: G11C 27/00 : Electric analogue stores, e.g. for storing instantaneous values
• CPC Class Codes: G11C 27/024 : using a capacitive memory element G11C27/04 takes precedence
• CPC Class Codes: G11C 27/04 : Shift registers
• CPC Class Codes: G11C 7/1042 : using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
• CPC Class Codes: G11C 7/16 : Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters

Abstract

An improved analog memory arrangement is interfaced to receive digital signals through a digital to analog converter and is interfaced to output analog signals through an analog to digital converter. Analog refreshing is implemented to reduce degradation of analog signals stored by the analog memory including scale factor refreshing and bias refreshing. The analog memory is particularly suitable for illumination signal processing and for storing display images to be displayed.

Claims

1. An analog memory system comprising:

a shiftable analog memory storing analog signals;

a shifting circuit coupled to the shiftable analog memory and shifting the analog signals stored by the shiftable analog memory;

an analog to digital converter coupled to the shiftable analog memory and generating digital output signals in response to the analog signals stored by the shiftable analog memory; and

a digital filter processor coupled to the analog to digital converter and generating filtered digital signal samples by filter processing the digital output signals, wherein the filter processor includes

a) a digital weighting circuit coupled to the analog to digital converter and generating weighted digital signal samples in response to the digital output signals and

b) a digital summing circuit coupled to the digital weighting circuit and generating filtered digital signal samples in response to the weighted digital signal samples.

2. An analog memory system as set forth in claim 1, wherein the shiftable analog memory includes an analog charge transfer device storing the analog signals.

3. An analog memory system as set forth in claim 1, wherein the shiftable analog memory includes an analog magnetic disk memory storing the analog signals.

4. An analog memory system as set forth in claim 1, wherein the shiftable analog memory includes an analog magnetic bubble memory storing the analog signals.

16. An analog memory system as set forth in claim 1, wherein the analog signals stored by the shiftable analog memory includes an analog stored program, wherein the digital output signals generated by the analog to digital converter include stored program digital output signals, and wherein the filter processor includes a stored program digital computer coupled to the analog to digital converter and processing the digital output signals by execution of the stored program digital output signals.

17. An analog memory system as set forth in claim 1, further comprising:

an analog input circuit coupled to the filter processor and generating analog input signals in response to the filtered digital signal samples; and

a writing circuit coupled to the analog input circuit and to the shiftable analog memory and writing the analog input signals into the shiftable analog memory.

18. An analog memory system as set forth in claim 1, further comprising:

a writing circuit coupled to the filter processor and to the shiftable analog memory and writing analog signals into the shiftable analog memory in response to the filtered digital signal samples.

5. An analog memory system comprising:

an analog memory storing analog signals;

a shifting circuit coupled to the analog memory and shifting the analog signals stored by the analog memory;

an analog refresh circuit coupled to the analog memory and refreshing the analog signals stored by the analog memory;

a converter coupled to the analog memory and generating digital output signals in response to the analog signals stored by the analog memory; and

a filter processor including a multiplier coupled to the converter and generating digital product signals in response to the digital output signals and an adder coupled to the multiplier and generating digital filtered signals by adding the digital product signals.

6. An analog memory system comprising:

a charge memory storing multiple state charge signals having an information content related to the signal state;

a refresh circuit coupled to the charge memory and refreshing the stored multiple state charge signals to reduce amplitude degradation;

a shifting circuit coupled to the charge memory and shifting the multiple state charge signals stored by the charge memory;

a converter coupled to the charge memory and generating digital output signals in response to the multiple state charge signals stored by the charge memory; and

a filter processor including a weighting circuit coupled to the converter and generating weighted digital signals in response to the digital output signals and an integrator coupled to the multiplier and generating digital filtered signals by integrating the digital product signals.

7. An analog memory system comprising:

a digital input circuit generating a digital input signal;

a digital to analog converter coupled to the input circuit and generating an analog input signal in response to the digital input signal;

an analog memory coupled to the digital to analog converter and storing the analog input signal;

a shifting circuit coupled to the analog memory and shifting the analog input signal stored by the analog memory;

an analog to digital converter coupled to the analog memory and generating a digital output signal in response to the analog input signal stored by the analog memory; and

a filter processor including a weighting circuit coupled to the analog to digital converter and generating a weighted digital signal in response to the digital output signal and a summer coupled to the multiplier and generating a digital filtered signal by summing the digital product signal.

10. An analog memory system as set forth in claim 7, wherein the analog input signal stored by the analog memory is a multiple state signal having an information content related to the signal state and wherein the analog memory includes a charge circuit storing the multiple state analog input signal as a multiple state charge signal;

wherein the system further comprises a refresh circuit coupled to the analog memory and refreshing the multiple state signal stored by the analog memory to reduce charge leakage degradation.

19. An analog memory system as set forth in claim 7, further comprising:

a digital to analog converter coupled to the analog to digital converter and generating an analog output signal and

an analog writing circuit coupled to the digital to analog converter and to the analog memory and writing the analog output signal into the analog memory.

21. An analog memory system as set forth in claim 7, wherein the analog memory includes an analog read only memory storing the analog signals.

22. An analog memory system as set forth in claim 7, wherein the analog memory is a charge transfer device memory storing the analog input signal as an analog charge signal.

23. An analog memory system as set forth in claim 7, wherein the analog memory is an analog magnetic bubble memory storing the analog input signal as an analog magnetic bubble signal.

24. An analog memory system as set forth in claim 7, wherein the analog memory is an analog magnetostrictive delay line memory storing the analog signal as an analog magnetostrictive signal.

8. An analog memory system comprising:

a digital input circuit generating a digital input signal;

a digital to analog converter coupled to the digital input circuit and generating an analog input signal in response to the digital input signal;

an analog memory coupled to the digital to analog converter and storing the analog input signal;

a shifting circuit coupled to the analog memory and shifting the analog input signal stored by the analog memory;

an analog to digital converter coupled to the analog memory and generating a digital output signal in response to the analog input signal stored by the analog memory;

a reference circuit generating an analog reference signal; and

a refresh circuit coupled to the analog memory and to the reference circuit and reducing degradation of the analog input signal stored by the analog memory in response to the analog reference signal.

9. An analog memory system comprising:

an analog read only memory storing an analog memory signal;

a shifting circuit coupled to the analog memory and shifting the analog memory signal stored by the analog read only memory; and

a filter processor including a weighting circuit coupled to the analog read only memory and generating a weighted analog signal in response to the analog memory signal stored by the analog read only memory and a summing circuit coupled to the weighting circuit and generating a filtered analog signal by summing the weighted analog signal.

11. An analog memory system comprising:

a digital input circuit generating a digital input signal;

a digital to analog converter coupled to the digital input circuit and generating an analog input signal in response to the digital input signal;

an analog memory coupled to the digital to analog converter and storing an analog signal in response to the analog input signal;

a shifting circuit coupled to the analog memory and shifting the analog signal stored by the analog memory;

an analog refresh circuit coupled to the analog memory and refreshing the analog signal stored by the analog memory;

an analog to digital converter coupled to the analog memory and generating a digital output signal in response to the analog signal stored by the analog memory; and

a filter processor coupled to the analog to digital converter and generating a weighted digital signal in response to the digital output signal and a summer coupled to the multiplier and generating a digital filtered signal by summing the digital product signal.

25. An analog memory system as set forth in claim 11, wherein amplitude of the analog signal stored by the analog memory is degraded by the storing thereby and wherein the system further comprises a refresh circuit coupled to the analog memory and reducing degradation of the stored analog signal.

28. An analog memory system as set forth in claim 11, wherein the analog signal stored by the analog memory includes a stored program, and wherein the filter processor includes a stored program digital computer coupled to the analog to digital converter and processing the digital output signal in response to the stored program.

29. An analog memory system as set forth in claim 11, further comprising a digital processor coupled to the analog to digital converter and processing digital data in response to the digital output signal.

30. An analog memory system as set forth in claim 11, further comprising a digital processor coupled to the analog to digital converter and processing digital data in response to the digital output signal, wherein the analog memory includes an analog writing circuit coupled to the digital to analog converter and writing the analog input signal into the analog memory.

12. An analog memory system comprising:

an analog memory storing analog signals, wherein the storing of the analog signals causes degradation of the analog signals;

a shifting circuit coupled to the analog memory and shifting the analog signals stored by the analog memory;

a refresh circuit coupled to the analog memory and refreshing the analog signals to reduce degradation thereof; and

a filter processor including a weighting circuit coupled to the analog memory and generating a weighted analog signal in response to the analog signals stored therein and a summing circuit coupled to the weighting circuit and generating a filtered analog signal by summing the weighted analog signal.

13. An analog memory system as set forth in claim 12, further comprising:

a digital input circuit generating digital input signals;

a digital to analog converter coupled to the digital input circuit and generating analog input signals in response to the digital input signal;

a writing circuit coupled to the analog memory and to the digital to analog to digital converter and writing the analog input signals into the analog memory; and

an analog to digital converter coupled to the analog memory and generating digital output signals in response to the analog signals stored by the analog memory.

14. An analog memory system as set forth in claim 12, further comprising:

a digital input circuit generating digital input signals;

a digital to analog converter coupled to the digital input circuit and generating analog input signals in response to the digital input signals; and

a writing circuit coupled to the digital to analog converter and to the analog memory and writing the analog input signals into the analog memory.

15. An analog memory system as set forth in claim 12, further comprising a digital output circuit connected to the analog memory and generating digital output signals in response to the analog signals stored by the analog memory.

20. An analog memory system comprising:

a digital input circuit generating a digital input signal;

a digital to analog converter coupled to the input circuit and generating an analog input signal in response to the digital input signal;

an analog memory coupled to the digital to analog converter and storing the analog input signal, wherein the analog input signal stored by the analog memory includes a stored program;

a shifting circuit coupled to the analog memory and shifting the analog input signal stored by the analog memory;

an analog to digital converter coupled to the analog memory and generating a digital output signal in response to the analog input signal stored by the analog memory; and

a stored program digital computer processing the digital output signal in response to the stored program stored by the analog memory.

26. An analog memory system comprising:

a digital input circuit generating a digital input signal;

.

a digital to analog converter coupled to the digital input circuit and generating an analog input signal in response to the digital input signal;

an analog memory coupled to the digital to analog converter and storing an analog signal in response to the analog input signal;

a shifting circuit coupled to the analog memory and shifting the analog signal stored by the analog memory;

an analog refresh circuit coupled to the analog memory and refreshing the analog signal stored by the analog memory, wherein the refresh circuit includes;

a converter circuit coupled to the analog memory and generating a digital number in response to the analog signal stored by the analog memory,

a compensation circuit coupled to the converter circuit and generating a compensated digital number by compensating the digital number for amplitude degradation, and

a converter coupled to the compensation circuit and generating a compensated analog signal in response to the compensated digital number; and

an analog to digital converter coupled to the analog memory and generating a digital output signal in response to the analog signal stored by the analog memory.

27. An analog memory system comprising:

a digital input circuit generating a digital input signal;

a digital to analog converter coupled to the digital input circuit and generating an analog input signal in response to the digital input signal;

an analog memory coupled to the digital to analog converter and storing an analog signal in response to the analog input signal;

a shifting circuit coupled to the analog memory and shifting the analog signal stored by the analog memory;

an analog refresh circuit coupled to the analog memory and refreshing the analog signal stored by the analog memory;

an analog to digital converter coupled to the analog memory and generating a digital output signal in response to the analog signal stored by the analog memory;

a digital processor coupled to the analog to digital converter and processing the digital output signal; and

a writing circuit coupled to the digital processor and to the analog memory and writing an analog signal into the analog memory in response to the digital output signal processed by the digital processor.

31. An analog memory system comprising:

a digital input circuit generating a digital input signal;

a digital to analog converter coupled to the input circuit and generating an analog input signal in response to the digital input signal;

an analog memory coupled to the digital to analog converter and storing the analog input signal;

a shifting circuit coupled to the analog memory and shifting the analog input signal stored by the analog memory;

a recirculation circuit coupled to the analog memory and recirculating the analog input signal stored by the analog memory;

a reference circuit coupled to the analog memory and generating an analog reference signal in response to the analog input signal stored by the analog memory; and

a refresh circuit coupled to the analog memory and to the reference circuit and reducing amplitude degradation of the analog input signal stored by the analog memory in response to the analog reference signal.

32. An analog memory system comprising:

a digital input circuit generating a digital input signal;

a digital to analog converter coupled to the digital input circuit and generating an analog input signal in response to the digital input signal;

an analog memory coupled to the digital to analog converter and storing the analog input signal;

a shifting circuit coupled to the analog memory and shifting the analog input signal stored by the analog memory;

a recirculation circuit coupled to the analog memory and recirculating the analog input signal stored by the analog memory;

an analog reference circuit generating an analog reference signal;

a refresh circuit coupled to the analog memory and to the analog reference circuit and refreshing the analog input signal stored by the analog memory to reduce degradation of the analog input signal in response to the analog reference signal; and

an analog to digital converter coupled to the analog memory and generating a digital output signal in response to the analog input signal stored by the analog memory.

33. An analog memory system comprising:

an analog memory storing an analog signal;

a shifting circuit coupled to the analog memory and shifting the analog signal stored by the analog memory;

an analog refresh circuit coupled to the analog memory and refreshing the analog signal stored by the analog memory;

a converter circuit coupled to the analog memory and generating a digital number in response to the analog signal stored by the analog memory;

a compensation circuit coupled to the converter circuit and generating a compensated digital number by compensating the digital number; and

a converter coupled to the compensation circuit and generating a compensated analog signal in response to the compensated digital number.

34. An analog memory system comprising:

an analog memory coupled to the digital to analog converter and storing the analog input signal;

a shifting circuit coupled to the analog memory and shifting the analog input signal stored by the analog memory;

a recirculation circuit coupled to the analog memory and recirculating the analog input signal stored by the analog memory;

a reference circuit coupled to the analog memory and generating a reference signal in response to the analog signal stored by the analog memory; and

a compensation circuit coupled to the analog memory and to the reference circuit and reducing degradation of the analog input signal stored by the analog memory in response to the reference signal.