Address buffer
First Claim
Patent Images
1. An address buffer in an integrated circuit, comprising:
- a first circuit which generates a true signal, wherein a delay occurs in generating the true signal; and
a second circuit which generates a complementary signal during normal operations of the integrated circuit, and during a special operating mode of the integrated circuit the second circuit generates a control signal that matches a voltage level of the true signal, wherein the second circuit includes a circuit which provides a delay in the second circuit that matches the delay in the first circuit.
1 Assignment
0 Petitions
Accused Products
Abstract
An address buffer which allows for the simultaneous selection and/or deselection of a plurality of rows and/or columns within a memory array. A first and a second circuit generate a true and a complementary signal, respectively, during normal operations of the integrated circuit. When desired, the first and second circuits may be used to generate two signals of the same voltage level. The two signals of the same voltage level may then be used by an address decoder to simultaneously select and/or deselect a plurality of rows and/or columns within a memory array.
-
Citations
23 Claims
-
1. An address buffer in an integrated circuit, comprising:
-
a first circuit which generates a true signal, wherein a delay occurs in generating the true signal; and a second circuit which generates a complementary signal during normal operations of the integrated circuit, and during a special operating mode of the integrated circuit the second circuit generates a control signal that matches a voltage level of the true signal, wherein the second circuit includes a circuit which provides a delay in the second circuit that matches the delay in the first circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 12, 21)
-
-
11. An address buffer in an integrated circuit, comprising:
-
a first circuit which generates a true signal during normal operations of the integrated circuits, and special operating mode of the integrated circuit the first circuit generates a first control signal, wherein the first circuit comprises a second inverter and a third inverter connected in series to the output of the at least one logic gate ; and a second circuit which generates a complementary signal during normal operations of the integrated circuit, and during a special operating mode of the integrated circuit the second circuit generates a second control signal, wherein the second circuit includes an input signal line;
a pass gate;
at least one logic gate connected in series between the input signal line and an input of the pass gate;
a first inverter connected to an output of the pass gate; and
a pull up transistor and a pull down transistor connected to the output of the pass gate, wherein the first and second control signals are set to the same voltage level.
-
-
13. An address buffer in an integrated circuit, comprising:
-
an input signal line; a pass gate; at least one logic gate connected in series between the input signal line and an input to the pass gate; a pull up transistor and a pull down transistor connected to an output of the pass gate, wherein the pull up and pull down transistors are used to generate a first control signal; and a first inverter and a second inverter connected in series to the output of the at least one logic gate, wherein the at least one logic gate, the first and second inverters are used to generate a second control signal, and wherein the first control signal and the second control signal are set to a single output voltage level during a special operating mode of the integrated circuit. - View Dependent Claims (14, 15, 16, 22)
-
-
17. An address buffer in an integrated circuit, comprising:
-
an input signal line; a pass gate; a first inverter and a second inverter connected in series between the input signal line and an input to the pass gate; a pull up transistor and a pull down transistor connected to an output of the pass gate, wherein the pull up and pull down transistors are used to generate a first control signal; and a third inverter and a fourth inverter connected in series to the output of the second inverter, wherein the first, second, third and fourth inverters are used to generate a second control signal, and wherein the first and second control signals are set to a single output voltage level during a special operating mode of the integrated circuit. - View Dependent Claims (18, 19, 20, 23)
-
Specification