Interface circuit for interfacing a peripheral device with a microprocessor operating in either a synchronous or an asynchronous mode
First Claim
1. An interface circuit for interfacing a peripheral device and a microprocessor to enable data transference between a microprocessor data bus and a memory location within the peripheral device, the interface circuit comprising:
- means for selecting an operating mode for the interface circuit, the operating mode being one of a synchronous mode and an asynchronous mode, whereby the interface circuit is operated in a synchronous mode when the microprocessor utilizes synchronous bus control and in an asynchronous mode when the microprocessor utilizes asynchronous bus control;
means for receiving a request for access to a peripheral memory location from the microprocessor;
means for providing the peripheral device with an address specifying the peripheral memory location being requested for access by the microprocessor;
means for receiving a clock signal from the microprocessor;
a temporary data storage register for temporarily storing data receiving from the microprocessor and the peripheral device;
means coupling the microprocessor data bus and the data storage register for data transference between the microprocessor data bus and the interface circuit;
means coupling the peripheral device and the data storage register for data transference between the interface circuit and the peripheral memory location;
means for receiving an indication from the peripheral device indicating that the peripheral device is engaged in transferring data between the data storage register and the peripheral memory location; and
control means responsive to the interface operating mode, the clock signal, the request for access from the microprocessor, and the indication of engagement in data transference from the peripheral device, for separately timing and controlling (A) data transference between the microprocessor data bus and the data storage register, and (B) data transference between the data storage register and the peripheral memory location.
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Accused Products
Abstract
An interface circuit is described for interfacing a peripheral device and a microprocessor to enable data transference between a memory location within the peripheral device and a data bus of the microprocessor. In accordance with the type of bus control used by the microprocessor, the interface circuit is operated in either a synchronous mode or an asynchronous mode. The interface includes a state machine that responds to the mode of interface operation, a clock signal provided by the microprocessor, requests from the microprocessor to access an addressed peripheral memory location, and a busy signal from the peripheral device indicating when the peripheral is engaged in transferring data between the interface circuit and an addressed peripheral memory location. Preferably, the interface also operates to detect error conditions based on changes in the access request during data transference between the microprocessor and the peripheral device. In response to detecting an error condition, the state machine acts to interrupt data transference to avoid the transfer of invalid data.
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Citations
15 Claims
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1. An interface circuit for interfacing a peripheral device and a microprocessor to enable data transference between a microprocessor data bus and a memory location within the peripheral device, the interface circuit comprising:
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means for selecting an operating mode for the interface circuit, the operating mode being one of a synchronous mode and an asynchronous mode, whereby the interface circuit is operated in a synchronous mode when the microprocessor utilizes synchronous bus control and in an asynchronous mode when the microprocessor utilizes asynchronous bus control; means for receiving a request for access to a peripheral memory location from the microprocessor; means for providing the peripheral device with an address specifying the peripheral memory location being requested for access by the microprocessor; means for receiving a clock signal from the microprocessor; a temporary data storage register for temporarily storing data receiving from the microprocessor and the peripheral device; means coupling the microprocessor data bus and the data storage register for data transference between the microprocessor data bus and the interface circuit; means coupling the peripheral device and the data storage register for data transference between the interface circuit and the peripheral memory location; means for receiving an indication from the peripheral device indicating that the peripheral device is engaged in transferring data between the data storage register and the peripheral memory location; and control means responsive to the interface operating mode, the clock signal, the request for access from the microprocessor, and the indication of engagement in data transference from the peripheral device, for separately timing and controlling (A) data transference between the microprocessor data bus and the data storage register, and (B) data transference between the data storage register and the peripheral memory location. - View Dependent Claims (2)
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3. An interface circuit for interfacing a peripheral device and a microprocessor to enable data transference between a microprocessor data bus and a memory location within the peripheral device, the interface circuit comprising:
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means for selecting an operating mode for the interface circuit, the operating mode being one of a synchronous mode and an asynchronous mode, whereby the interface circuit is operated in a synchronous mode when the microprocessor utilizes synchronous bus control and in an asynchronous mode when the microprocessor utilizes asynchronous bus control; means for receiving a request from the microprocessor for access to a peripheral memory location, the request including a select signal for selecting the peripheral device for access, an address signal specifying the peripheral memory location, and a read/write signal for indicating whether the request is for a read access or a write access; means for receiving a clock signal from the microprocessor; means for latching the address signal and for sending a corresponding latched address signal to the peripheral device; a temporary data storage register for temporarily storing data received from the microprocessor and the peripheral device; means for coupling the microprocessor data bus and the temporary data storage register for transferring data between the microprocessor data bus and the temporary data storage register; means for coupling the peripheral device and the data storage register for transferring data between the data storage register and the peripheral memory location; means for receiving a busy signal from the peripheral device indicating when the peripheral device is engaged in data transference between the temporary data storage register and the peripheral memory location; and control means responsive to the interface operating mode, the clock signal, the select signal, the read/write signal, and the busy signal for separately timing and controlling (A) data transference between the microprocessor data bus and the temporary data storage register, and (B) data transference between the temporary data storage register and the peripheral memory location. - View Dependent Claims (4, 5, 6, 7, 8)
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9. An interface circuit for interfacing a peripheral device and a microprocessor to enable data transference between a microprocessor data bus and a memory location within the peripheral device, the interface circuit comprising:
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means for selecting an operating mode for the interface circuit, the operating mode being one of a synchronous mode and an asynchronous mode, whereby the interface circuit is operated in a synchronous mode when the microprocessor utilizes synchronous bus control and in an asynchronous mode when the microprocessor utilizes asynchronous bus control; means for receiving a request from the microprocessor for access to a peripheral memory location, the request including a select signal for selecting the peripheral device for access, an address signal specifying the peripheral memory location, and a read/write signal for indicating whether the request is for a read access or a write access; means for receiving a clock signal from the microprocessor; means for latching the address signal and for sending a corresponding latched address signal to the peripheral device; a temporary data storage register for temporarily storing data received from the microprocessor and the peripheral device; means coupled the peripheral device and the temporary data storage register for transferring multiple bytes of data in parallel between the temporary data storage register and the peripheral memory location; means for coupling the microprocessor data bus and the temporary data storage register for separately transferring single bytes of data between the microprocessor data bus and the temporary data storage register; means for receiving a busy signal from the peripheral device indicating when the peripheral device is engaged in transferring multiple bytes of data between the temporary data storage register and the peripheral memory location; and control means responsive to the interface operating mode, the clock signal, the select signal, the read/write signal, and the busy signal for separately timing and controlling multiple transference of single byte data between the microprocessor data bus and the temporary data storage register, and multiple byte data transference between the temporary data storage register and the peripheral memory location. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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Specification