Method and apparatus for reducing checking costs in fault tolerant processors

• US 5,339,408 A
• Filed: 12/30/1992
• Issued: 08/16/1994
• Est. Priority Date: 12/30/1992
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Digital Equipment Corporation (HP Inc.)
• Inventors: Bruckert, William, Paternoster, Paul, Bissett, Thomas D., Dearth, Glenn
• Primary Examiner(s): Canney, Vincent P.
• Application Number:
  US07/998,715
• Time in Patent Office: 594 Days
• Field of Search: 395/578, 395/200, 395/325, 395/373, 371/9.1, 371/11.3, 371/12, 371/16.5, 371/68.3
• US Class Current: 714/11
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution
• CPC Class Codes: G06F 11/1604 where the fault affects the clock signals of a processing unit and the redundancy is at or within the level of clock signal generation hardware
• CPC Class Codes: G06F 11/1633 using mutual exchange of the output between the redundant processing components
• CPC Class Codes: G06F 11/1645 and the comparison itself uses redundant hardware
• CPC Class Codes: G06F 11/1654 where the output of only one of the redundant processing components can drive the attached hardware, e.g. memory or I/O
• CPC Class Codes: G06F 11/1658 Data re-synchronization of a redundant component, or initial sync of replacement, additional or spare unit
• CPC Class Codes: G06F 11/1679 at clock signal level
• CPC Class Codes: G06F 11/1683 at instruction level
• CPC Class Codes: G06F 11/20 using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
• CPC Class Codes: G06F 11/2205 using arrangements specific to the hardware being tested
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: H03D 13/003 in which both oscillations are converted by logic means into pulses which are applied to filtering or integrating means
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/089 the phase or frequency detector generating up-down pulses H03L7/087 takes precedence

Abstract

According to one aspect of the invention, an apparatus includes a first processor coupled to a first system bus to provide data to a cache and a memory, and a second processor coupled to the first system bus and a second abbreviated system bus to receive read data from said first system bus. In accordance with a further aspect of the invention, an apparatus includes means for correcting errors in memory. In accordance with a further aspect of the invention, an apparatus includes a number of computing systems each including a memory device mounted on an infrequently replaced hardware unit, and capable of communicating with the number of computing systems. In accordance with another aspect of the invention, an apparatus includes a counter, means for detecting a selected state of said counter, and means, responsive to output signals from said counter, for selectively permitting or inhibitting transfer of data fed to a recirculating state device. In accordance with a further aspect of the invention, an apparatus includes a first means for providing a first clocking signal, a second means for providing a second clocking signal, means for providing an error signal responsive to an offset between edges of the first and second clocking signals.

Claims

1. An apparatus comprising:

a central processing unit comprising;

first and second processors to process an identical instruction stream;

a data bus coupled to said first and second processors;

means for providing said first processor to furnish data to said data bus and to receive data from said data bus in response to said identical instruction stream; and

means for providing said second processor to receive data from said data bus in response to said identical instruction stream.

2. The apparatus of claim 1 further comprising:

a first system bus comprising an address bus, a control bus, an error code bus and said data bus, coupled to said first processor, to provide data to a cache and a memory;

a second abbreviated system bus comprising an address bus, a control bus, and an error code bus, coupled to said second processor to provide data to said cache and said memory;

error checking means for comparing said corresponding busses of said first system bus to said second abbreviated system bus to detect inconsistencies; and

error correction means for comparing said an error code of said data bus with said error code bus of said first system bus to check and correct errors in said data bus.

3. The apparatus of claim 1 further comprising:

a cache comprising;

a cache memory coupled to said data bus to store data provided by said first processor;

first and second tag storage means for storing addresses provided by and received by said first and second processors respectively in response to said identical instruction stream; and

first and second error code storage means for storing error codes provided by and received by said first and second processors respectively in response to said identical instruction stream.

4. The apparatus of claim 1 further comprising:

a main memory further comprising;

first and second memory control means for storing a first and second address and a control data provided by said first and second processors respectively in response to said identical instruction stream;

first error storage means for storing a first error code provided by said first in response to said identical instruction stream;

data storage means for storing data provided from said first processor on said data bus; and

error checking means for comparing said first and second address data, said first and second control data, and said first and second error code data.

5. The apparatus of claim 4, wherein said error checking means compares said first and second data to detect an inconsistency between address, control and error data provided by the first and second processors.

6. The apparatus of claim 4 further comprising error detection means for generating an error code from data stored in said data storage means and for comparing said generated error code to said first error code.

7. The apparatus of claim 1, further comprising a plurality of said computer processing systems operating on said identical instruction stream simultaneously.

8. An apparatus comprising:

a central processing unit comprising;

first and second processors to process an identical instruction stream;

a first system bus comprising a data bus coupled to said first and second processors with said first processor providing data to said data bus and receiving data from said data bus in response to said identical instruction stream and said second processor receiving data from said data bus and checking said data on said data bus for accuracy, said first system bus further comprising;

a first address bus, a first error bus and a first control bus coupled to said first processor; and

with said apparatus further comprising

a second abbreviated system bus coupled to said second processor comprising a second address bus, a second error bus and a second control bus, and said data bus of said first system bus.

9. The apparatus of claim 8 further comprising:

a cache comprising;

a cache memory coupled to said data bus, said first address bus and said first control bus;

first and second tag storage means for storing data on said first and second address bus and said first and second control bus respectively; and

first and second error storage means for storing data on said first and second error busses respectively.

10. The apparatus of claim 8 further comprising:

a main memory further comprising;

first and second memory control means for storing a first data on said first and second address and said first and second control bus respectively;

first and second error storage means for storing data on said first and second error code busses respectively;

data storage means for storing data on said data bus;

error checking means for comparing said address and control data from said first and second tag storage means, and for comparing data from said first and second error storage means; and

error detection means for generating an error code from data stored in said data storage means and for comparing said generated error code to said data stored in said first error storage means.

11. The apparatus of claim 8, further comprising a plurality of said computer processing systems operating on said identical instruction stream simultaneously.