High speed sample and hold circuit and radio constructed therewith

• US 5,339,459 A
• Filed: 12/03/1992
• Issued: 08/16/1994
• Est. Priority Date: 12/03/1992
• Status: Expired due to Term

• Current Assignee: Voice Signals LLC (Intellectual Ventures LLC)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Schiltz, Thomas E., Nuckolls, Carl R.
• Primary Examiner(s): Eisenzopf, Reinhard J.
• Assistant Examiner(s): VO, NGUYEN THANH
• Application Number:
  US07/985,477
• Time in Patent Office: 621 Days
• Field of Search: 455/313, 455/318, 455/323, 455/319, 455/343, 455/333, 455/334, 455/316, 307/352, 307/353, 328/151
• US Class Current: 455/333
• CPC Class Codes: G11C 27/026 associated with an amplifier G11C27/028 takes precedence
• CPC Class Codes: H04B 1/0003 Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain digital baseband systems H04L25/00; digital modulation/demodulation H04L27/00; CDMA H04B1/707; TDMA H04B7/2643; image transmission H04N5/00
• CPC Class Codes: H04B 1/0014 using DSP [Digital Signal Processor] quadrature modulation and demodulation
• CPC Class Codes: H04B 1/0025 using a sampling rate lower than twice the highest frequency component of the sampled signal for demodulation of angle-modulated signals H03D3/006
• CPC Class Codes: H04B 1/0039 using DSP [Digital Signal Processor] quadrature modulation and demodulation
• CPC Class Codes: H04B 1/26 for superheterodyne receivers multiple frequency-changing H03D7/16

Abstract

A sample and hold circuit is formed within an integrated circuit and has a small, substantially linear hold capacitance. The circuit includes a sampling switch, a hold capacitor, and a buffer amplifier. The buffer amplifier includes a common drain FET and a constant current source FET. The common drain FET provides an input which couples to the hold capacitor. The constant current FET isolates the source of the common drain FET from ground. The sample and hold circuit may be used as a wide bandwidth mixer. In a radio application, a pulse generator provides a stream of pulses in which the sampling rate times an integer number equals the RF frequency minus the IF frequency. The width of the sampling pulse is less than the period of an RF signal. In an oscillator application, the sample and hold circuit operates as a mixer in a frequency multiplying phase locked loop.

Claims

1. A radio comprising:

an antenna for supplying an RF signal exhibiting an RF frequency;

a sample and hold circuit having a sample input coupled to said antenna, having a control input, and having a hold output for supplying an IF signal;

a pulse generator having an output coupled to said control input of said sample and hold circuit, said pulse generator being configured to produce a stream of pulses at a sampling rate less than said RF frequency and configured so that each of said pulses has a pulse width substantially less than a period of said RF signal; and

wherein said sample and hold circuit comprises;

a sampling switch having a first port serving as said sample input, a second port serving as said control input, and a third port;

a hold capacitor coupled to said third port of said sampling switch; and

a buffer amplifier having an input coupled to said third port of said sampling switch and having an output serving as said hold output; and

wherein said buffer amplifier comprises;

a first transistor configured in a common drain circuit arrangement, having a gate coupled to said third port of said sampling switch, and having a source and a drain; and

a second transistor configured as a constant current source, said second transistor being coupled to said source of said first transistor; and

wherein said second transistor has a drain and a source, and said circuit additionally comprises;

a first resistor coupled between said source of said first transistor and said drain of said second transistor, said first resistor exhibiting a first resistance;

a second resistor coupled to said source of said second transistor, said second resistor exhibiting a second resistance which substantially equals said first resistance;

a first terminal for receiving a relatively positive voltage, said first terminal being coupled to said first transistor drain; and

a second terminal for receiving a relatively negative voltage, said second terminal being coupled to said second transistor source via said second resistor.

4. A radio as claimed in claim 1 wherein said pulse generator is further configured so that said sampling rate is less than approximately one-half of said RF frequency.

5. A radio as claimed in claim 1 wherein said pulse generator is further configured so that said sampling rate times an integer number substantially equals said RF frequency plus or minus an IF frequency of said IF signal.

6. A radio as claimed in claim 1 additionally comprising an image filter coupled between said antenna and said sample and hold circuit.

7. A radio as claimed in claim 1 wherein said sampling switch, said hold capacitor, and said buffer amplifier are all formed within a common integrated circuit.

8. A radio as claimed in claim 1 wherein each of said sampling switch, said hold capacitor, and said buffer amplifier are formed on a common GaAs die.

9. A radio as claimed in claim 1 wherein said third port of said sampling switch, said input of said buffer amplifier, and at least a portion of said hold capacitor reside within an area less than five-thousandths of a square inch.

10. A radio as claimed in claim 1 wherein:

said sample and hold circuit additionally comprises a terminal which is adapted to receive a common potential;

said hold capacitor additionally couples to said terminal;

said buffer amplifier exhibits an input capacitance between said buffer amplifier input and said terminal; and

said hold capacitor is configured to exhibit a capacitance substantially greater than said buffer amplifier input capacitance.

2. A high speed sample and hold circuit comprising:

a sampling switch having an input for receiving a signal to be sampled and having an output;

a hold capacitor coupled to said sampling switch output;

a first transistor configured in a common drain circuit arrangement, having a gate coupled to said sampling switch output and having a source;

a second transistor having a drain and a source, said second transistor configured as a substantially constant current source, said second transistor being coupled to said source of said first transistor, wherein said sampling switch, hold capacitor, first transistor and second transistor each reside within a common integrated circuit;

a first resistor residing within said common integrated circuit and being coupled between said source of said first transistor and said drain of said second transistor;

a second resistor residing within said common integrated circuit and being coupled to said source of said second transistor;

a first external contact of said common integrated circuit coupled to said source of said first transistor; and

a second external contact of said common integrated circuit coupled to said drain of said second transistor.

11. A high speed sample and hold circuit as claimed in claim 2 wherein said first transistor additionally has a drain, said first and second resistors exhibit substantially equivalent resistances, and said circuit additionally comprises:

a third external contact of said common integrated circuit for receiving a relatively positive voltage, said third external contact being coupled to said first transistor drain; and

a fourth external contact of said common integrated circuit for receiving a relatively negative voltage, said fourth external contact being coupled to said source of said second transistor via said second resistor.

12. A high speed sample and hold circuit as claimed in claim 11 additionally comprising:

a terminal within said common integrated circuit which is adapted to receive a common potential;

a first biasing resistor included within said common integrated circuit and being coupled between said gate of said first transistor and said terminal; and

a second biasing resistor included within said common integrated circuit and being coupled between said gate of said second transistor and said fourth external contact of said common integrated circuit.

13. A high speed sample and hold circuit as claimed in claim 2 wherein:

said circuit additionally comprises a terminal within said common integrated circuit which is adapted to receive a common potential;

said hold capacitor additionally couples to said terminal;

said common drain circuit arrangement exhibits an input capacitance between said gate of said first transistor and said terminal; and

said hold capacitor is configured to exhibit a capacitance substantially greater than said input capacitance.

14. A high speed sample and hold circuit as claimed in claim 2 wherein said sampling switch, said hold capacitor, said first transistor, and said second transistor all reside within an area less than five-thousandths of a square inch.

17. A high speed sample and hold circuit as claimed in claim 2 wherein said common integrated circuit is formed on a common GaAs die.

3. In a system comprising a sampling switch, a hold capacitor and a buffer amplifier, wherein:

said sampling switch comprises an input for receiving a signal to be sampled, an output and a sampling signal input port coupled to a pulse generator for receiving a stream of pulses at a sampling rate;

said hold capacitor is coupled to said sampling switch output; and

said buffer amplifier comprises a first transistor configured in a common drain circuit arrangement, having a gate coupled to said output of said sampling switch and having a source and a drain, and a second transistor having a drain and a source, said second transistor being configured as a constant current source coupled via a first resistor exhibiting a first resistance coupled between said source of said first transistor and said drain of said second transistor, a second resistor coupled to said source of said second transistor, said second resistor exhibiting a second resistance which substantially equals said first resistance, a first terminal for receiving a relatively positive voltage, said first terminal coupled to said first transistor drain, a second terminal for receiving a relatively negative voltage, said second terminal coupled to said second transistor source via said second resistor,

a method for generating an IF signal exhibiting an IF frequency, said method comprising steps of;

supplying an RF signal exhibiting an RF period to said input of said sampling switch;

successively sampling, in response to said stream of pulses coupled to said sampling signal input port, said RF signal by said sampling switch to generate a stream of RF samples, said sampling rate causing less than one sample to be taken per RF period, and said sampling occurring for each sample over a duration which is substantially less than said RF period; and

holding by said hold capacitor, each of said RF samples between successive ones of said samples.

15. A method as claimed in claim 3 wherein said sampling step causes said sampling rate to be less than approximately one-half of said RF frequency.

16. A method as claimed in claim 3 wherein said sampling step is configured so that said sampling rate times an integer number substantially equals a frequency of said RF signal minus said IF frequency.