Short channel trenched DMOS transistor

• US 5,341,011 A
• Filed: 03/15/1993
• Issued: 08/23/1994
• Est. Priority Date: 03/15/1993
• Status: Expired due to Term

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Hshieh, Fwu-Iuan, Yilmaz, Hamza, Chang, Mike F.
• Primary Examiner(s): LIMANEK, ROBERT P
• Application Number:
  US08/031,798
• Time in Patent Office: 526 Days
• Field of Search: 257/329, 257/330, 257/331, 257/332, 257/335
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: Y10S 148/103 Mask, dual function, e.g. diffusion and oxidation
• CPC Class Codes: Y10S 438/965 Shaped junction formation

Abstract

A DMOS transistor having a trenched gate is formed in a substrate such that the P body region of the transistor may be formed heavier or deeper while still maintaining a "short" channel. This is accomplished by forming a portion of the N+ type source region within the P body region prior to forming the trench, followed by a second implantation and diffusion of a relatively shallow extension of the N+ source region formed overlying a part of the P body region. The increased depth or doping concentration of the P body region advantageously lowers the resistance of the P body region, while the short channel lowers the on-resistance of the transistor for improved performance.

Claims

1. A trenched transistor comprising:

a substrate of a first conductivity type defining a trench containing a conductive gate electrode;

a body region of a second conductivity type extending from a principal surface of the substrate adjacent to the trench into the substrate to a depth less than that of the trench, wherein a portion of the body region immediately adjacent to the trench is shallower with respect to the principal surface than is another portion of the body region away from the trench, an edge of the body region immediately adjacent the trench sloping such that a portion of the edge immediately adjacent the trench is closer to the principal surface; and

a source region of the first conductivity type formed in the substrate.

2. The transistor of claim 1, wherein the source region extends from the principal surface adjacent to the trench into the substrate to a depth less than that of the body region, the source region being deeper immediately adjacent to the trench and shallower away from the trench with respect to the principal surface.

3. The transistor of claim 1, wherein the source region is deeper immediately adjacent to said trench and shallower away from said trench, with respect to the principal surface.

4. The transistor of claim 1, wherein the body region is shallower with respect to the principal surface immediately adjacent to the trench and deeper away from said trench.

5. The transistor of claim 1, further comprising a deep body region of the second conductivity type extending from the principal surface of the substrate and being of a higher doping concentration than the body region, the deep body region being disposed away from the trench and formed substantially within the body region.

7. The transistor of claim 1, wherein prior to forming the trench, a portion of the source region is implanted and diffused into the body region through the principal surface laterally defined by a mask so as to cause a depth reduction of a portion of the body region between the portion of the source region and the substrate, the portion of the body region with the depth reduction determining a short channel.

8. The transistor of claim 7, wherein said mask is used to etch the trench.

9. The transistor of claim 7, wherein said trench is deeper than the body region with respect to the principal surface.

10. The transistor of claim 7, wherein said portion of the source region is shallowly extended laterally along the principal surface on either side of the trench to form the source region.

11. The transistor of claim 10, wherein a heavy dose of dopant is implanted and diffused to form said shallow extension of the portion of the source region.

6. A trenched transistor comprising:

a substrate of a first conductivity type defining a trench containing a conductive gate electrode;

a body region of a second conductivity type extending from a principal surface of the substrate adjacent to the trench into the substrate to a depth less than that of the trench, wherein a portion of the body region immediately adjacent to the trench has an edged which is sloping such that a portion of the edge immediately adjacent the trench is shallower with respect to the principal surface than is another edge portion of the body region away from the trench; and

a source region of the first conductivity type formed in the substrate, the source region extending from the principal surface adjacent to the trench into the substrate to a depth less than that of the body region, the source region being deeper immediately adjacent to the trench and shallower away from the trench with respect to the principal surface.