CMOS device for use in connection with an active matrix panel

• US 5,341,012 A
• Filed: 07/31/1992
• Issued: 08/23/1994
• Est. Priority Date: 05/17/1988
• Status: Expired due to Term

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Oshima, Hiroyuki, Misawa, Toshiyuki
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): TRAN, MINH LOAN
• Application Number:
  US07/923,751
• Time in Patent Office: 753 Days
• Field of Search: 257/347, 257/351, 257/352, 257/72, 257/66, 257/369, 359/59, 359/54, 359/87
• US Class Current: 257/351
• CPC Class Codes: G02F 1/133345 Insulating layers G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence
• CPC Class Codes: G02F 1/13454 Drivers integrated on the active matrix substrate G02F1/136277 takes precedence
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 1/136254 Checking; Testing
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2300/0809 Several active elements per pixel in active matrix panels
• CPC Class Codes: G09G 2330/12 Test circuits or failure detection circuits included in a display system, as permanent part thereof
• CPC Class Codes: G09G 3/001 using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background slide projectors per se G03B23/00 = 42 HP
• CPC Class Codes: G09G 3/002 to project the image of a two-dimensional display, such as an array of light emitting or modulating elements or a CRT
• CPC Class Codes: G09G 3/003 to produce spatial visual effects
• CPC Class Codes: G09G 3/006 Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309
• CPC Class Codes: G09G 3/2011 by amplitude modulation
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3659 the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G09G 3/3688 suitable for active matrices only
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/8592 Applying permanent coating, e.g. protective coating
• CPC Class Codes: H01L 23/4825 for devices consisting of semiconductor layers on insulating or semi-insulating substrates, e.g. silicon on sapphire devices, i.e. SOS
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/78618 : characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: Y10S 257/923 : with means to optimize electrical conductor current carrying capacity, e.g. particular conductor aspect ratio
• CPC Class Codes: Y10S 345/904 : Display with fail/safe testing feature

Abstract

An active matrix panel including a matrix of driving electrodes couples through thin film transistor switches to a corresponding source line and gate line and at least one of a driver circuit including complementary thin film transistors for driving the source and/or gate lines of the picture elements on the substrate. The thin film transistors of the active matrix have the same cross-sectional structure as the P-type or the N-type thin film transistors forming the driver circuit and are formed during the same patterning process.

Claims

1. A CMOS device, comprising:

a substrate;

a thin silicon film carried by said substrate;

a thin film transistor formed from said thin silicon film, and carried by the substrate, said thin film transistor having a source region and a drain region formed from at least a first type of impurity; and

a second transistor, formed from said thin silicon film, and carried by the substrate, said second transistor having a source region and a drain region formed from at least said first type of impurity and a second type of impurity;

wherein the concentrations of the first type of impurity and second type of impurity are different from each other.

2. The CMOS device of claim 1, wherein the thin film transistor is a P-type having source and drain regions formed from at least acceptor impurities and the second transistor is an N-type having source and drain regions formed from at least donor impurities, the concentration of donor impurities in the second transistor being greater than the concentration of acceptor impurities in the thin film transistor.

3. The CMOS device of claim 1, wherein the thin film transistor is an N-type having source and drain regions formed from at least donor impurities and the second transistor is a P-type having source and drain regions formed from at least acceptor impurities, the concentration of acceptor impurities in the second transistor being greater than the concentration of donor impurities in the thin film transistor.