Basic cell for BiCMOS gate array

• US 5,341,041 A
• Filed: 08/08/1991
• Issued: 08/23/1994
• Est. Priority Date: 05/15/1990
• Status: Expired due to Fees

• Current Assignee: Arm Physical IP, Inc. (SoftBank Group Corp.)
• Original Assignee: Siarc, Inc.
• Inventors: El Gamal, Abbas
• Primary Examiner(s): Pascal, Robert J.
• Assistant Examiner(s): RATLIFF, REGINALD A
• Application Number:
  US07/743,532
• Time in Patent Office: 1,111 Days
• Field of Search: 307/465, 307/468, 307/465.1, 307/466, 307/443, 307/446, 257/204, 257/206, 257/207, 257/209
• US Class Current: 326/44
• CPC Class Codes: H01L 27/11896 using combined field effect/bipolar technology
• CPC Class Codes: H03K 19/09448 in combination with bipolar transistors [BIMOS]
• CPC Class Codes: H03K 19/1735 by wiring, e.g. uncommitted logic arrays

Abstract

An improved cell for use in a mask programmable gate array is disclosed herein. The preferred cell comprises two compute sections, each comprising two pairs of medium size P and N-channel transistors, two small N-channel transistors, and a single small P-channel transistor. Each cell also comprises a high efficiency drive section containing a single bipolar pull-up transistor, a large N-channel pull-down transistor, and a small P-channel transistor. By using this cell, an extremely high compute capability per die area is achieved.

Claims

1. A cell for use in a mask programmable array comprising:

one or more small size P-channel transistors;

two or more medium size P-channel transistors;

two or more small size N-channel transistors;

two or more medium size N-channel transistors; and

one or more large size N-channel transistors;

said medium size P-channel transistors having a channel width at least approximately twice the size of said small size P-channel transistors, said medium size N-channel transistors having a channel width at least approximately twice the size of said small size N-channel transistors, said channel width of said small size P-channel transistors being equal to or narrower than said channel width of said small size N-channel transistors, said large size N-channel transistors having a channel width larger than the channel width of said medium size N-channel transistors,

gates of said one or more small size N-channel transistors being isolated from gates of said one or more small and medium size P-channel transistors,

wherein said cell is one of a plurality of identical cells located within an interior of said mask programmable array.

2. In a programmed BiCMOS gate array containing a plurality of programmed BiCMOS cells, each of said BiCMOS cells comprising:

a plurality of P-channel transistors;

two or more sizes of N-channel transistors; and

one or more NPN bipolar transistors, each of said one or more NPN bipolar transistors sharing an N-well with one or more of said P-channel transistors so that said NPN bipolar transistors may only be used as pull-up devices,

said BiCMOS cells containing no PNP bipolar transistors,

said BiCMOS cells being formed internal to said gate array.

3. The BiCMOS cells of claim 2 wherein said one or more NPN bipolar transistors comprise only one NPN bipolar transistor.

4. The BiCMOS cells of claim 2 wherein certain ones of said N-channel transistors are located within said cell so as to allow an adjacent identical BiCMOS cell in an array of BiCMOS cells to share said certain ones of said N-channel transistors.

5. The BiCMOS cells of claim 4 wherein said certain ones of said N-channel transistors are for use as additional pull-down devices in a macrocell formed formed by the interconnection of components in said adjacent identical cell, said pull-down devices for driving an output of said macrocell to a low state.

6. In a programmed BiCMOS gate array containing a plurality of programmed BiCMOS cells, each of said BiCMOS cells comprising:

a plurality of P-channel transistors;

a plurality of N-channel transistors; and

one more more bipolar transistors, each of said one or more bipolar transistors sharing an N-well with one or more of said P-channel transistors as that said bipolar transistors may only be used as pull-up devices,

wherein said plurality of P-channel transistors comprises two or more sizes of P-channel transistors, where a size corresponds to a channel width,

wherein said plurality of N-channel transistors comprise three or more sizes of N-channel transistors, where a size corresponds to a channel width, and

wherein said cells are internal to said gate array.

7. The BiCMOS cells of claim 6 wherein said P-channel transistors comprise at least one medium size P-channel transistor and at least one small size P-channel transistor, wherein said small size P-channel transistor is smaller than said medium size P-channel transistor;

and

said N-channel transistors comprise at least one small size N-channel transistor, at least one medium size N-channel transistor, and at lest one large size N-channel transistor, wherein said small size N-channel transistor has a greater current handling capability than said at least one medium size P-channel transistor, wherein said medium size N-channel transistor is larger than said small size N-channel transistor, and wherein said large size N-channel transistor is larger than said medium size N-channel transistor.

8. The BiCMOS cells of claim 7 wherein said one or more bipolar transistors comprise only one bipolar transistor.

9. An integrated circuit containing an array of programmed BiCMOS cells, one or more said cells comprising one or more substantially rectangular compute sections and one or more drive sections, each drive section comprising one or more bipolar transistors for use as pull-up devices in one or more macrocells, and one or more N-channel transistors for use as pull-down devices in said one or more macrocells for driving an output of said one or more macrocells to a low state, each compute section comprising components which may be interconnected to form a two-to-one multiplexer, said multiplexer having true and complement outputs, said true output being equal to a power supply voltage, said complement output being equal to ground potential.

10. The BiCMOS cells of claim 9 wherein each of said compute sections contains components which may be interconnected to form a D latch having a D input terminal, a clock input terminal, and an inverted clock input terminal, such that when a clock signal applied to said clock input terminal is high, an output of said latch corresponds to a D input signal applied to said D input terminal of said latch, and when said clock signal is low, said output of said latch is unchanged.

11. The BiCMOS cells of claim 9 wherein two of said compute sections contains components which may be interconnected to form a dual port SRAM cell, each port being independently useable to read or write contents of said SRAM cell.

12. The BiCMOS cells of claim 9 wherein two of said compute sections contain components which may be interconnected to form a master/slave D flip-flop having a D input terminal, a clock input terminal, and an inverted clock input terminal.

13. The BiCMOS cells of claim 9 wherein two of said compute sections contain components which may be interconnected to form any two-input logic gate with true and complement outputs, said true output being equal to a power supply voltage, said complement output being equal to ground potential.

14. The BiCMOS cells of claim 9 wherein two of said compute sections contain components which may be interconnected to form two SRAM memory cells.

15. The BiCMOS cells of claim 9 wherein each of said drive sections further comprises one or more P-channel transistors.

16. The BiCMOS cells of claim 9 wherein said compute sections within said cell are identical to one another.

17. The BiCMOS cells of claim 9 wherein said N-channel transistors for use as pull-down devices are located within said cell so as to allow an adjacent identical BiCMOS cell in an array of BiCMOS cells to share said N-channel transistors.

18. The BiCMOS cells of claim 17 wherein said N-channel transistors are for use as additional pull-down devices in a macrocell formed by the interconnection of components in said adjacent identical cell, said pull-down devices for driving an output of said macrocell to a low state.

19. In a programmed gate array containing a plurality of programmed cells, each of said cells comprising;

one or more substantially rectangular compute sections and one or more drive sections, each of said drive sections containing one or more MOS transistors which are substantially larger than MOS transistors within said compute sections, each compute section comprising;

two or more sizes of P-channel transistors, where a size corresponds to a channel width; and

two or more sizes of N-channel transistors;

wherein said P-channel transistors comprise at least two medium size P-channel transistors and at least one small size P-channel transistors, wherein said small size P-channel transistor is smaller than each of said medium size P-channel transistor; and

said N-channel transistors comprise at least two small size N-channel transistors and at least two medium size N-channel transistors, wherein each of said small size N-channel transistors has a greater current handling capability than each of said at least two medium size P-channel transistors, and wherein each of said medium size N-channel transistors is larger than each of said small size N-channel transistors.

20. The cells of claim 19 wherein each of said at least two medium size N-channel transistors is at least approximately twice as large as each of said at least two small size N-channel transistors.

21. The cells of claim 20 wherein each of said compute sections comprises:

two of said medium size P-channel transistors;

one or more of said small size P-channel transistors;

two of said medium size N-channel transistors; and

two of said small size N-channel transistors.

22. The cells of claim 19 wherein each of said drive sections comprise one or more bipolar transistors for use as pull-up device sin macrocells for driving an output of said macrocells to a high state and one or more N-channel divides for use as pull-down divides in macrocells for driving an output of said macrocells to a low state.

23. The cells of claim 22 wherein each drive section further comprises one or more P-channel transistors.

24. The cells of claim 19 wherein certain ones of said MOS transistors within said drive sections are located so as to allow an adjacent identical cell in an array of cells to share said certain ones of said MOS transistors.

25. The cells of claim 24 wherein said certain ones of said MOS transistors are for use as additional pull-down devices in a macrocell formed by the interconnection of components in said adjacent identical cell, said pull-down devices for driving an output of said macrocell to a low state.

26. The cells of claim 19 wherein each of said one or more drive sections comprises a first transistor for providing pull-up drive current in a single programmed cell and a second transistor for providing pull-down drive current in said single programmed cell.

27. The cells of claim 26 wherein said first transistor is a bipolar transistor.

28. The cells of claim 27 wherein said second transistor is an N-channel MOS transistor.

29. In a programmed BiCMOS gate array, one or more macrocells having one or more bipolar transistors being used as pull-up devices and no bipolar transistors being used as pull-down devices, wherein said pull-up devices are for driving an output of said one or more macrocells to a high state,

wherein said one or more macrocells are formed by the interconnection of components within one or more BICMOS cells in an unprogrammed BiCMOS gate array, each of said BiCMOS cells comprising one or more compute sections and one or more drive sections, each of said one or more drive sections including said one or more bipolar transistors, and each of said compute sections comprising a plurality of P-channel transistors, a plural of N-channel transistors, and no bipolar transistors.

30. The programmed BiCMOS gate array of claim 29 wherein said plurality of P-channel transistors comprise P-channel transistors of two or more different channel widths, and wherein said plurality of N-channel transistors comprise N-channel transistors of two or more different channel widths.

31. In a programmed BiCMOS gate array, one or more macrocells having one or more bipolar transistors being used as pull-up devices and no bipolar transistors being used as pull-down devices, wherein said pull-up devices are for driving an output of said one or more macrocells to a high state,

wherein said one or more macrocells are formed by the interconnection of components within one or more BiCMOS cells in an unprogrammed BiCMOS gate array, each of said BiCMOS cells comprising one or more substantially rectangular compute sections and one or more drive sections, each of said drive sections comprising:

one or more bipolar transistors for use as pull-up devices in said one or more macrocells for driving an output of said one or more macrocells to a high state, and one or more N-channel transistors for use as pull-down devices in said one or more macrocells for driving an output of said one or more macrocells to a low state.

32. The programmed BiCMOS gate array of claim 31 wherein two drive sections are adjacent to one another to allow components within adjacent drive sections to be interconnected to increase current drive capabilities for a single macrocell.

33. The programmed BiCMOS state array of claim 31 wherein at least one of said one or more N-channel transistors in each of said drive sections has a greater current handling capability than any N-channel transistors within said compute sections.

34. The programmed BiCMOS gate array of claim 31 wherein two or more compute sections are directly adjacent to each other, with one of said two or more compute sections adjacent to a single drive section so that components within said two or more compute sections and components within said single drive section may be interconnected to form a single macrocell.

35. An integrated circuit containing an array of unprogrammed BiCMOS cells, one or more of said cells comprising one or more substantially rectangular compute sections and one or more drive sections, each drive section comprising three or more drive transistors for use as drive transistors in a single macrocell, said three or more drive transistors being programmably connectable so as to provide said macrocell with a variety of pull-up or pull-down driving capabilities.

36. The integrated circuit of claim 35 wherein said three or more transistors comprise a plurality of transistors for use as pull-up transistors in a single macrocell and one or more transistors for use as pull-down transistors in said single macrocell, said plurality of pull-up transistors being programmably connectable so as to provide said macrocell with a variety of output driving capabilities.

37. The integrated circuit of claim 36 wherein said plurality of transistors for use as pull-up transistors comprises a plurality of bipolar transistors.

38. The integrated circuit of claim 35 wherein said three or more transistors comprise one or more transistors for use as pull-up transistors in a single macrocell and a plurality of transistors for use as pull-down transistors in said single macrocell, said plurality of pull-down transistors being programmably connectable so as to provide said macrocell with a variety of output driving capabilities.

39. The integrated circuit of claim 38 wherein said plurality of transistors for use as pull-down transistors comprises a plurality of N-channel transistors.

40. The integrated circuit of claim 35 wherein said three or more transistors comprise a plurality of transistors for use as pull-up transistors in a single macrocell and a plurality of transistors for use as pull-down transistors in said single macrocell, said plurality of pull-up and pull-down transistors being programmably connectable so as to provide said macrocell with a variety of output driving capabilities.

41. The integrated circuit of claim 40 wherein said pull-up transistors comprise a plurality of bipolar transistors.

42. The integrated circuit of claim 40 wherein said pull-down transistors comprise a plurality of N-channel transistors.