Integrated limiter and amplifying devices
First Claim
1. A high power limiter for a low noise amplifier, comprising a substrate, a first anti-parallel array of Schottky diodes monolithically integrated on said substrate and comprising first and second Schottky diodes arranged in parallel and in reverse polarity relative to each other between a first input node and a first output node, a conductor on said substrate having a first end providing a limiter input for receiving a signal and a second end providing a limiter output for connection to said low noise amplifier, said first input node being coupled to said conductor intermediate said first and second ends of said conductor, said first output node being coupled to a ground reference, a second anti-parallel array of Schottky diodes monolithically integrated on said substrate and coupled in series with said first anti-parallel array between said conductor and said ground reference, said second anti-parallel array comprising third and fourth Schottky diodes arranged in parallel and in reverse polarity relative to each other between a second input node and a second output node, said second input node being coupled to said first output node, said second output node being coupled to said ground reference.
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Accused Products
Abstract
Integrated circuit structure and processing is provided for a high power limiter including at least a first anti-parallel array of monolithically integrated Schottky diodes. In a further embodiment, integrated circuit structure and processing is provided for an MMIC, microwave and millimeter wave monolithic integrated circuit, including an amplifier and a high power limiter monolithically integrated on the same substrate.
34 Citations
12 Claims
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1. A high power limiter for a low noise amplifier, comprising a substrate, a first anti-parallel array of Schottky diodes monolithically integrated on said substrate and comprising first and second Schottky diodes arranged in parallel and in reverse polarity relative to each other between a first input node and a first output node, a conductor on said substrate having a first end providing a limiter input for receiving a signal and a second end providing a limiter output for connection to said low noise amplifier, said first input node being coupled to said conductor intermediate said first and second ends of said conductor, said first output node being coupled to a ground reference, a second anti-parallel array of Schottky diodes monolithically integrated on said substrate and coupled in series with said first anti-parallel array between said conductor and said ground reference, said second anti-parallel array comprising third and fourth Schottky diodes arranged in parallel and in reverse polarity relative to each other between a second input node and a second output node, said second input node being coupled to said first output node, said second output node being coupled to said ground reference.
- 2. A high power limiter for a low noise amplifier, comprising a substrate, a first anti-parallel array of Schottky diodes monolithically integrated on said substrate and comprising first and second Schottky diodes arranged in parallel and in reverse polarity relative to each other between a first input node and a first output node, a conductor on said substrate having a first end providing a limiter input for receiving a signal and a second end providing a limiter output for connection to said low noise amplifier, said first input node being coupled to said conductor intermediate said first and second ends of said conductor, said first output node being coupled to a ground reference, a second anti-parallel array of Schottky diodes monolithically integrated on said substrate and coupled in parallel with said first anti-parallel array between said conductor and said ground reference, said second anti-parallel array comprising third and fourth Schottky diodes arranged in parallel and in reverse polarity relative to each other between a second input node and a second output node, said second input node being coupled to said conductor intermediate said first and second ends of said conductor, said second output node being coupled to said ground reference.
- 4. A high power limiter providing impedance transformation and matching for a low noise amplifier without a separate noise matching network, comprising a substrate, a first anti-parallel array of Schottky diodes monolithically integrated on said substrate and comprising first and second Schottky diodes arranged in parallel and in reverse polarity relative to each other between a first input node and a first output node, a conductor on said substrate having a first end providing a limiter input for receiving a signal and a second end providing a limiter output for connection to said low noise amplifier, said first input node being coupled to said conductor intermediate said first and second ends of said conductor, said first output node being coupled to a ground reference, said conductor including inductor means transforming the impedance at said first end to a different impedance at said second end matching said low noise amplifier, such that said limiter has unequal input and output impedances, the output impedance being less than the input impedance.
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6. A high power limiter providing impedance transformation and matching for a low noise amplifier without a separate noise matching network, comprising a substrate, a first anti-parallel array of Schottky diodes monolithically integrated on said substrate and comprising first and second Schottky diodes arranged in parallel and in reverse polarity relative to each other between a first input node and a first output node, a conductor on said substrate having a first end providing a limiter input for receiving a signal and a second end providing a limiter output for connection to said low noise amplifier, said first input node being coupled to said conductor intermediate said first and second ends of said conductor, said first output node being coupled to a ground reference, said conductor including inductor means transforming the impedance at said first end to a different impedance at said second end matching said low noise amplifier, wherein said inductor means comprises first and second inductors connected in series with each other between said first and second ends of said conductor, and wherein said first input node is coupled to said conductor intermediate said first and second inductors, and comprising a third Schottky diode and first and second resonating capacitors monolithically integrated on said substrate, said first resonating capacitor and said first anti-parallel array being connected in series between said ground reference and said conductor intermediate said first and second inductors, said first resonating capacitor tuning out the parasitic inductance of said first and second Schottky diodes to reduce the reactive portion of the diode impedance, said third Schottky diode and said second resonating capacitor being connected in series between said ground reference and said conductor intermediate said second inductor and said second conductor end, said second resonating capacitor tuning out the parasitic inductance of said third Schottky diode to reduce the reactive portion of the diode impedance.
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7. A high power limiter for a low noise amplifier, comprising a substrate, a first anti-parallel array of Schottky diodes monolithically integrated on said substrate and comprising first and second Schottky diodes arranged in parallel and in reverse polarity relative to each other between a first input node and a first output node, a conductor on said substrate having a first end providing a limiter input for receiving a signal and a second end providing a limiter output for connection to said low noise amplifier, said conductor comprising first and second inductors connected in series with each other between said first and second ends of said conductor, said first input node being coupled to said conductor intermediate said first and second inductors, said first output node being coupled to a ground reference, first and second capacitors and a third Schottky diode monolithically integrated on said substrate, said first capacitor and said first anti-parallel array being connected in series between said ground reference and said conductor intermediate said first and second inductors, said second capacitor and said third Schottky diode being conducted in series between said ground reference and said conductor intermediate said second inductor and said second end of said conductor.
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8. A high power limiter for a low noise amplifier, comprising a substrate, a conductor on said substrate having a first end providing a limiter input for receiving a signal and a second end providing a limiter output for connection to said low noise amplifier and including first and second inductors connected in series with each other between said-first and second ends of said conductor and including a first connection node between said first and second inductors and a second connection node between said second inductor and said second end of said conductor, first, second and third capacitors monolithically integrated on said substrate, first, second, third and fourth anti-parallel arrays of Schottky diodes monolithically integrated on said substrate, said first anti-parallel array comprising first and second Schottky diodes arranged in parallel and in reverse polarity relative to each other between a first input node and a first output node, said second anti-parallel array comprising third and fourth Schottky diodes arranged in parallel and in reverse polarity relative to each other between a second input node and a second output node, said third anti-parallel array comprising fifth and sixth Schottky diodes arranged in parallel and in reverse polarity relative to each other between a third input node and a third output node, said fourth anti-parallel array comprising seventh and eighth Schottky diodes arranged in parallel and in reverse polarity relative to each other between a fourth input node and a fourth output node, a ninth Schottky diode monolithically integrated on said substrate and coupled in series with said third capacitor between said second connection node and a ground reference, said first capacitor being connected between said first connection node and said first input node, said first output node being connected to said second input node, said second output node being connected to said ground reference, said second capacitor being connected between said first connection node and said third input node, said third output node being connected to said fourth input node, said fourth output node being connected to said ground reference.
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9. A high power limiter for a low noise amplifier comprising a substrate, an odd number of Schottky diodes monolithically integrated on said substrate comprising a first anti-parallel array of Schottky diodes comprising first and second Schottky diodes arranged in parallel and in reverse polarity relative to each other between a first input node and a first output node, a conductor on said substrate having a first end providing a limiter input for receiving a signal and a second end providing a limiter output for connection to said low noise amplifier, said first input node being coupled to said conductor intermediate said first and second ends of said conductor, said first output node being coupled to a ground reference, a third said Schottky diode coupled between said ground reference and said conductor, said third Schottky diode being the odd Schottky diode, wherein said first anti-parallel array is coupled to said conductor at a first connection node, said third Schottky diode is coupled to said conductor at a second connection node, and said conductor includes an inductor between said first and second connection nodes.
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10. A high power limiter for a low noise amplifier comprising a substrate, an odd number of Schottky diodes monolithically integrated on said substrate comprising a first anti-parallel array of Schottky diodes comprising first and second Schottky diodes arranged in parallel and in reverse polarity relative to each other between a first input node and a first output node, a conductor on said substrate having a first end providing a limiter input for receiving a signal and a second end providing a limiter output for connection to said low noise amplifier, said first input node being coupled to said conductor intermediate said first and second ends of said conductor, said first output node being coupled to a ground reference, a third said Schottky diode coupled between said ground reference and said conductor, said third Schottky diode being the odd Schottky diode, wherein said first anti-parallel array is coupled to said conductor at a first connection node, said third Schottky diode is coupled to said conductor at a second connection node, and said conductor includes first and second inductors connected in series with each other between said first and second ends of said conductor, said first inductor being between said first end of said conductor and said first connection node, said second inductor being between said first connection node and said second connection node, said second connection node being between said second inductor and said second end of said conductor.
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11. An MMIC, microwave and millimeter wave monolithic integrated circuit, comprising a substrate, an amplifier monolithically integrated on said substrate, a high power limiter integrated on the same said substrate with said amplifier, wherein said limiter comprises a plurality of Schottky diodes, wherein said amplifier comprises a FET, field effect transistor, monolithically integrated on said substrate and having a junction, and comprising a first anti-parallel array of Schottky diodes monolithically integrated on said substrate and comprising a first and second Schottky diodes arranged in parallel and in reverse polarity relative to each other between a first input node and a first output node, a conductor on said substrate having a first end providing a limiter input for receiving a signal and a second end providing a limiter output coupled to said FET, said first input node being coupled to said conductor intermediate said first and second ends of said conductor, said first input node being coupled to a ground reference, and comprising a third Schottky diode monolithically integrated on said substrate, wherein said third Schottky diode and said junction are in parallel and in reverse polarity relative to each other to form a second anti-parallel array of diodes, wherein said FET comprises a gate, source and drain, and wherein said third Schottky diode is arranged in parallel and in reverse polarity with the gate to source junction of said FET, and comprising first and second resonating capacitors monolithically integrated on said substrate, said first resonating capacitor being connected in series with said first anti-parallel array between said conductor and said ground reference and tuning out the parasitic inductance of said first and second Schottky diodes to reduce the reactive portion of the diode impedance, said second resonating capacitor being connected in series with said third Schottky diode between said conductor and said ground reference and tuning out the parasitic inductance of said third Schottky diode to reduce the reactive portion of the diode impedance.
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12. An MMIC, microwave and millimeter wave monolithic integrated circuit, comprising a substrate, an amplifier monolithically integrated on said substrate, a high power limiter integrated on the same said substrate with said amplifier, wherein said limiter comprises a plurality of Schottky diodes, wherein said amplifier comprises a FET, field effect transistor, monolithically integrated on said substrate and having a junction, and comprising a first anti-parallel array of Schottky diodes monolithically integrated on said substrate and comprising a first and second Schottky diodes arranged in parallel and in reverse polarity relative to each other between a first input node and a first output node, a conductor on said substrate having a first end providing a limiter input for receiving a signal and a second end providing a limiter output coupled to said FET, said first input node being coupled to said conductor intermediate said first and second ends of said conductor, said first output node being coupled to a ground reference, and comprising a third Schottky diode monolithically integrated on said substrate, wherein said third Schottky diode and said junction are in parallel and in reverse polarity relative to each other to form a second anti-parallel array of diodes, wherein said FET comprises a gate, source and drain, and wherein said third Schottky diode is arranged in parallel and in reverse polarity with the gate to source junction of said FET, and wherein said first anti-parallel array is coupled to said conductor at a first connection node, and said third Schottky diode is coupled to said conductor at a second connection node, and said conductor includes first and second inductors connected in series with each other between said first and second ends of said conductor, said first inductor being between said first end of said conductor and said first connection node, said second inductor being between said first connection node and said second connection node, said second connection node being between said second inductor and said gate of said FET.
Specification