Video signals clamping circuit for maintaining DC level of video signals

• US 5,341,218 A
• Filed: 04/07/1992
• Issued: 08/23/1994
• Est. Priority Date: 04/09/1991
• Status: Expired due to Term

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Ookuma, Ikuo, Kaneko, Hideki, Inoue, Sadayuki
• Primary Examiner(s): Peng, John K.
• Application Number:
  US07/864,679
• Time in Patent Office: 868 Days
• Field of Search: 358/171, 358/172, 358/34
• US Class Current: 348/695
• CPC Class Codes: H04N 5/185 for the black level

Abstract

A video signal clamping circuit capable of maintaining a DC level of a digital video signal at a fixed level, in which a pedestal level in a vertical blanking period of the digital video signal after an A/D conversion is sampled, and an average value of a plurality of sampling data in a plurality of fields is calculated by an average value calculator. The average value is compared with a predetermined clamp level reference value by a comparison output circuit, and depending on the comparison result, a signal either added or subtracted by a certain width to or from an output signal of a predetermined period before is output for automatically controlling a clamp voltage.

Claims

1. A video signal clamping circuit for maintaining a DC level of a digital video signal at a fixed level, comprising:

an A/D converter for converting an input analog video signal into the digital video signal;

a first latch circuit for sampling a predetermined part of the digital video signal at a predetermined period and latching the sampled data;

an average value calculator circuit for taking in a predetermined number of the sampled data items latched by the first latch circuit and calculating an average value of the sampled data;

a comparison output circuit for comparing the average value obtained in the average value calculator circuit with a reference value and outputting data either added or subtracted by a predetermined width to or from an output signal of a predetermined period before depending on a comparison result;

a D/A converter for converting the data output by the comparison output circuit into an analog signal; and

a clamp voltage supply means for supplying a clamp voltage to the input analog video signal on the basis of the analog signal output by the D/A converter, wherein the clamp voltage supply means includes a level compression shift for carrying out a level compression so that a voltage variation amount of the output of the D/A converter corresponding to 1 LSB of change of the input of the D/A converter is less than a voltage variation amount of 1 LSB change of the output of the A/D converter, and for shifting the voltage level to a predetermined level.

2. The circuit of claim 1, wherein the clamp voltage supply means further includes a buffer means for stabilizing the output of the level compression shift circuit, and a hold means for holding an output of the buffer means at a predetermined period and supplying the clamp voltage to the analog video signal input to the A/D converter.

3. The circuit of claim 1, further comprising a second latch circuit for latching the output of the comparison output circuit at a predetermined period and supplying the output to the D/A converter.

4. The circuit of claim 1, further comprising first control signal generator means for generating a first control signal for determining a sampling timing of the first latch circuit and a take-in timing of the average value calculator circuit on the basis of a vertical synchronizing signal of the input analog video signal to supply data in a pedestal period of the analog video signal to the average value calculator circuit.

5. The circuit of claim 4, further comprising second control signal generator means for generating a second control signal for determining a number of data taken from the first latch circuit into the average value calculator circuit.

6. The circuit of claim 1, further comprising variation width detector means for detecting a variation width of the output of the first latch circuit to change a number of data taken in the average value calculator circuit according to the variation width.

7. The circuit of claim 6, wherein the variation width detector means includes first and second comparators for comparing the variation width with first and second reference values, respectively, to detect the variation width from the comparison results of the two comparators.

8. The circuit of claim 1, further comprising variation width detector means for detecting a variation width of the output of the first latch circuit and mask processor means for masking predetermined decimal bits of data of the output of the average value calculator circuit, to change a number of the bits masked by the mask processor means depending on the detection result of the variation width detector means.

9. The circuit of claim 8, wherein the variation width detector means includes first and second comparators for comparing the variation width with first and second reference values, respectively, to detect the variation width from the comparison results of the two comparators.

10. The circuit of claim 9, wherein the average value calculator circuit includes an accumulator for accumulating a predetermined number of the the sampled data, an adder for adding a predetermined offset value to an output of the accumulator, and an offset value generator for generating the predetermined offset value.

11. The circuit of claim 10, the offset value generator changes the generated offset value depending on the detection result of the variation width detector means.