Test pattern generation device

• US 5,341,315 A
• Filed: 03/13/1992
• Issued: 08/23/1994
• Est. Priority Date: 03/14/1991
• Status: Expired due to Fees

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Niwa, Hisao, Kayashima, Kazuhiro
• Primary Examiner(s): Harvey, Jack B.
• Assistant Examiner(s): STAMBER, ERIC W
• Application Number:
  US07/850,877
• Time in Patent Office: 893 Days
• Field of Search: 371/23, 371/27, 364/551.1, 364/579, 364/580
• US Class Current: 714/738
• CPC Class Codes: G01R 31/318307 computer-aided, e.g. automatic test program generator [ATPG], program translations, test program debugging

Abstract

A test pattern generation device for producing test pattern signals for testing a preselected digital circuit includes a dominant pattern signal generator and a subservient pattern signal generator. When a first dominant pattern signal (0,0,0,0,0) is generated, five subservient pattern signals (1,0,0,0,0), (0,1,0,0,0), (0,0,1,0,0), (0,0,0,1,0) and (0,0,0,0,1) are generated, each being unit Hamming distance from the dominant pattern signal. The subservient pattern signals are sequentially applied to a simulator carrying a hypothetical digital circuit for producing a controllability cost CCO_f and a continuous cyclic logic value CV_f at a preselected line G_f in the digital circuit for each subservient pattern signal. A cost generator produces an evaluation cost CT_f by the use of the controllability cost CCO_f and the continuous cyclic logic value CV_f for each subservient pattern signal. A selector selects from the set of subservient pattern signals a subservient pattern signal that produced a minimum evaluation cost CT_f, test pattern memory stores the selected subservient pattern signal as one test pattern and assigns the selected subservient pattern signal as a next dominant pattern signal in a next cycle operation.

Claims

1. A test pattern generation device for producing test pattern signals for testing a preselected digital circuit having a preselected line comprising:

means for producing a dominant pattern signal in a binary form;

means for producing a set of subservient pattern signals from said dominant pattern, each of said subservient pattern signals having a binary form and being unit Hamming distance from said dominant pattern signal;

means, responsive to each subservient pattern, for simulating an operation of the preselected digital circuit which produces a result;

means for producing, from the result of the simulation operation, a controllability cost at the preselected line in said digital circuit for each of said subservient pattern signals;

means for producing, from the result of the simulation operation, a continuous cyclic logic value at said preselected line for each of said subservient pattern signals, said continuous cyclic logic value having a continuous value which changes from logic "0" to logic "1", logic "1" to logic "unknown X", and logic "unknown X" to logic "0", said continuous logic value having a first distance from logic "0" to logic "unknown X" equal to a second distance from logic "unknown X" to logic "1", which is in turn equal to a third distance from logic "0" to logic "1";

means for producing an evaluation cost at said preselected line by the use of said controllability cost and said continuous cyclic logic value for each subservient pattern signal;

means for selecting from said set of subservient pattern signals the subservient pattern signal that produced a minimum evaluation cost; and

test pattern memory means for storing said selected subservient pattern signal as one test pattern and assigning said selected subservient pattern signal as a next dominant pattern signal in a next cycle operation.

2. A test pattern generation device according to claim 1, wherein said selecting means comprises a memory for storing said minimum evaluation cost CT_f for comparing the minimum evaluation cost CT_f obtained in the previous cycle operation and that obtained in the present cycle operation, said selecting means selecting said subservient pattern signal from the present cycle operation when said minimum evaluation cost CT_f obtained in the present cycle is smaller than that obtained in the previous cycle, and selecting a modified subservient pattern signal, which is a subservient pattern signal selected in the previous cycle with one bit representing a clock bit being changed, when said minimum evaluation cost CT_f obtained in the present cycle is not smaller than that obtained in the previous cycle.

3. A test pattern generation device according to claim 1, wherein said simulating means produces at an output of each element, a controllability cost CCO_i which represents the number of steps necessary to change the present output condition to logic "0", a controllability cost CC1_i which represents the number of steps necessary to change the present output condition to logic "1", a controllability cost CCP_i which represents the number of steps necessary to change the present output condition first to logic "0" and then to logic "1", and a controllability cost CCN_i which represents the number of steps necessary to change the present output condition first to logic "1" and then to logic "0".

4. A test pattern generation device according to claim 1, wherein said evaluation cost producing means produces said evaluation cost CT_f by the following equation:

space="preserve" listing-type="equation">CT.sub.f =K1×

CCT.sub.f +K2×

CCV.sub.f

wherein K1 and K2 are predetermined constants, CCT_f is a controllability cost which represents the number of steps necessary to change the present output condition to logic "T", and CCV_f is a difference between the continuous cyclic logic value CV_f and a desired continuous cyclic logic value DCV_f of the preselected line G_f.

5. A test pattern generation device according to claim 1, wherein said means for producing said continuous cyclic logic value is a neural network.