Method for stress testing decoders and periphery circuits

• US 5,341,336 A
• Filed: 04/30/1993
• Issued: 08/23/1994
• Est. Priority Date: 04/30/1993
• Status: Expired due to Term

• Current Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Original Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Inventors: McClure, David C.
• Primary Examiner(s): LaRoche, Eugene R.
• Assistant Examiner(s): NIRANJAN, FRANK
• Application Number:
  US08/056,376
• Time in Patent Office: 480 Days
• Field of Search: 365/201, 365/230.08, 365/189.05, 365/230.08, 365/201
• US Class Current: 365/201
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters

Abstract

A method for stress testing decoders and other periphery circuits used with a memory array. An address buffer simultaneously sets the inputs of a plurality of decoders to a first common voltage level, so that a plurality of rows and/or columns within the memory array are selected for a predetermined period of time. A stress voltage is then applied to the integrated circuit to stress test the gate oxides within the decoders and other periphery circuits. The inputs of the plurality of decoders are then simultaneously set to a second common voltage level, so that the plurality of rows and/or columns within the memory array are deselected. Finally, a stress voltage is applied to the integrated circuit to stress test the gate oxides within the decoders and other periphery circuits.

Claims

1. A method for stress testing decoders and periphery circuits used with a memory array in an integrated circuit, comprising the steps of:

simultaneously setting the inputs of a plurality of row decoding circuits to a first common voltage level, wherein a plurality of rows within the memory array are selected for a predetermined period of time;

applying a stress voltage to the integrated circuit;

simultaneously setting the inputs of the plurality of row decoding circuits to a second common voltage level, wherein the plurality of rows within the memory array are deselected; and

applying a stress voltage to the integrated circuit.

2. The method of claim 1, further comprising the step of placing the integrated circuit in a test or special operating mode prior to performing the step of simultaneously setting the inputs of a plurality of row decoding circuits to a first common voltage level.

3. The method of claim 1, wherein said step of simultaneously setting the inputs of the plurality of row decoding circuits to the first common voltage level further comprises the step of simultaneously setting the inputs of a plurality of column decoding circuits to the first common voltage level, wherein a plurality of bit and complementary bit lines within the memory array are selected for a predetermined period of time.

4. The method of claim 3, wherein the step of simultaneously setting the inputs of the plurality of row decoding circuits to the second common voltage level further comprises the step of simultaneously setting the inputs of a plurality of column decoding circuits to the second common voltage level, wherein the plurality of bit and complementary bit lines within the memory array are deselected.

5. The method of claim 1, wherein said step of simultaneously setting the inputs of the plurality of row decoding circuits to the first common voltage level comprises simultaneously setting the inputs of the plurality of row decoding circuits to a high voltage level.

6. The method of claim 5, wherein said step of simultaneously setting the inputs of the plurality of row decoding circuits to the second common voltage level comprises simultaneously setting the inputs of the plurality of row decoding circuits to a low voltage level.

7. A method for stress testing decoders and periphery circuits used with a memory array in an integrated circuit, comprising the steps of:

simultaneously setting the inputs of a plurality of row decoding circuits to a first common voltage level, wherein a plurality of rows within the memory array are selected for a predetermined period of time, wherein a bit line load of a bit line pair is turned off during selection of a plurality of rows;

applying a stress voltage to the integrated circuit;

simultaneously setting the inputs of the plurality of row decoding circuits to a second common voltage level, wherein the plurality of rows within the memory array are deselected; and

applying a stress voltage to the integrated circuit.

8. The method of claim 7, wherein the bit line load is pulled to ground after being turned off.

9. A method for stress testing decoders and periphery circuits used with a memory array in an integrated circuit, comprising the steps of:

simultaneously setting the inputs of a plurality of row decoding circuits to a first common voltage level, wherein a plurality of rows within the memory array are selected for a predetermined period of time;

applying a stress voltage to the integrated circuit;

simultaneously setting the inputs of the plurality of row decoding circuits to a second common voltage level, wherein the plurality of rows within the memory array are deselected; and

applying a stress voltage to the integrated circuit;

wherein said steps of setting the inputs of a plurality of row decoding circuits or column decoding circuits are performed when the stress voltage is set to a low voltage level.

10. A method for stress testing decoders and periphery circuits used with a memory array in an integrated circuit, comprising the steps of:

simultaneously setting the inputs of a plurality of column decoding circuits to a first common voltage level, wherein a plurality of bit and complementary bit lines within the memory array are selected for a predetermined period of time;

applying a stress voltage to the integrated circuit;

simultaneously setting the inputs of the plurality of column decoding circuits to a second common voltage level, wherein the plurality of bit and complementary bit lines within the memory array are deselected; and

applying a stress voltage to the integrated circuit.

11. The method of claim 10, further comprising the step of placing the integrated circuit in a test or special operating mode prior to performing the step of simultaneously setting the inputs of a plurality of column decoding circuits to a first common voltage level.

12. The method of claim 10, wherein said step of simultaneously setting the inputs of the plurality of column decoding circuits to the first common voltage level further comprises the step of simultaneously setting the inputs of a plurality of row decoding circuits to the first common voltage level, wherein a plurality of rows within the memory array are selected for a predetermined period of time.

15. The method of claim 12, wherein the step of simultaneously setting the inputs of the plurality of column decoding circuits to the second common voltage level further comprises the step of simultaneously setting the inputs of a plurality of row decoding circuits to the second common voltage level, wherein the plurality of rows within the memory array are deselected.

16. The method of claim 10, wherein said step of simultaneously setting the inputs of the plurality of column decoding circuits to the first common voltage level comprises simultaneously setting the inputs of the plurality of column decoding circuits to a high voltage level.

17. The method of claim 16, wherein said step of simultaneously setting the inputs of the plurality of column decoding circuits to the second common voltage level comprises simultaneously setting the inputs of the plurality of column decoding circuits to a low voltage level.

13. A method for stress testing decoders and periphery circuits used with a memory array in an integrated circuit, comprising the steps of:

simultaneously setting the inputs of a plurality of column decoding circuits to a first common voltage level, wherein a plurality of bit and complementary bit lines within the memory array are selected for a predetermined period of time and simultaneously setting the inputs of a plurality of row decoding circuits to the first common voltage level, wherein a plurality of rows within the memory array are selected for a predetermined period of time;

applying a stress voltage to the integrated circuit;

simultaneously setting the inputs of the plurality of column decoding circuits to a second common voltage level, wherein the plurality of bit and complementary bit lines within the memory array are deselected; and

applying a stress voltage to the integrated circuit;

wherein a bit line load of a bit line pair is turned off during selection of the plurality of rows.

14. The method of claim 13, wherein the bit line load is pulled to ground after being turned off.

18. A method for stress testing decoders and periphery circuits used with a memory array in an integrated circuit, comprising the steps of:

simultaneously setting the inputs of a plurality of column decoding circuits to a first common voltage level, wherein a plurality of bit and complementary bit lines within the memory array are selected for a predetermined period of time and simultaneously setting the inputs of a plurality of row decoding circuits to the first common voltage level, wherein a plurality of rows within the memory array are selected for a predetermined period of time;

applying a stress voltage to the integrated circuit;

simultaneously setting the inputs of the plurality of column decoding circuits to a second common voltage level, wherein the plurality of bit and complementary bit lines within the memory array are deselected; and

applying a stress voltage to the integrated circuit;

wherein said steps of setting the inputs of a plurality of row decoding circuits or column decoding circuits are performed when the stress voltage is set to a low voltage level.

19. A method for stress testing decoders and periphery circuits used with a memory array in an integrated circuit, comprising the steps of:

simultaneously setting the inputs of a plurality of row decoding circuits to a first common voltage level, wherein a plurality of rows within the memory array are selected for a predetermined period of time;

simultaneously setting the inputs of a plurality of column decoding circuits to a second common voltage level, wherein a plurality of bit and complementary bit lines within the memory array are selected for the predetermined period of time;

applying a stress voltage to the integrated circuit;

simultaneously setting the inputs of the plurality of row decoding circuits to a third common voltage level, wherein the plurality of rows within the memory array are deselected;

simultaneously setting the inputs of the plurality of column decoding circuits to a fourth common voltage level, wherein the plurality of bit and complementary bit lines within the memory array are deselected; and

applying a stress voltage to the integrated circuit.

20. The method of claim 19, further comprising the step of placing the integrated circuit in a test or special operating mode prior to performing the step of simultaneously setting the inputs of a plurality of row decoding circuits to a first common voltage level.

21. The method of claim 19, wherein said step of simultaneously setting the inputs of a plurality of row decoding circuits to the first common voltage level comprises simultaneously setting the inputs of a plurality of row decoding circuits to a low voltage level.

22. The method of claim 19, wherein said step of simultaneously setting the inputs of a plurality of column decoding circuits to the second common voltage level comprises simultaneously setting the inputs of a plurality of column decoding circuits to a low voltage level.

23. The method of claim 19, wherein said step of simultaneously setting the inputs of a plurality of row decoding circuits to the third common voltage level comprises simultaneously setting the inputs of a plurality of row decoding circuits to a high voltage level.

24. The method of claim 19, wherein said step of simultaneously setting the inputs of a plurality of column decoding circuits to the fourth common voltage level comprises simultaneously setting the inputs of a plurality of column decoding circuits to a high voltage level.

25. The method of claim 19, wherein a bit line load of a bit line pair is turned off during selection of a plurality of rows.

26. The method of claim 25, wherein the bit line load is pulled to ground after being turned off.

27. The method of claim 19, wherein said steps of setting the inputs of a plurality of row decoding circuits or column decoding circuits are performed when the stress voltage is set to a low voltage level.