Communication interface

• US 5,341,371 A
• Filed: 05/24/1991
• Issued: 08/23/1994
• Est. Priority Date: 05/25/1990
• Status: Expired due to Term

• Current Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Original Assignee: Inmos Limited (STMicroelectronics NV)
• Inventors: Simpson, Robert J.
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): TON, DANG T
• Application Number:
  US07/705,186
• Time in Patent Office: 1,187 Days
• Field of Search: 370/85.4, 370/85.1, 370/85.11, 370/105.1, 370/105.4, 370/94.1, 370/85.9, 370/85.5, 371/49.1, 371/32, 371/33, 371/57.1, 371/49.2, 371/49.3, 371/49.4, 371/50.1, 371/51.1, 364/405, 375/38, 375/113, 360/40, 360/48
• US Class Current: 370/438
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence
• CPC Class Codes: H04L 1/0063 Single parity check
• CPC Class Codes: H04L 1/0083 Formatting with frames or packets; Protocol or part of protocol for error control
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04L 7/0037 Delay of clock signal
• CPC Class Codes: H04L 7/0041 Delay of data signal
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04L 7/048 using the properties of error detecting or error correcting codes, e.g. parity as synchronisation signal

Abstract

A communication interface for interconnecting a computer with at least one other device has a link output circuit and a link input circuit. A link output on one device is connected to a link input on another device by a data line and a parallel strobe line. Data is transmitted on the data line in serial bit strings forming a succession of tokens of predetermined lengths. Signal transitions are provided on the parallel strobe line where no signal transition occurs on the data line. Each token includes a bit indicating the length of the token and a parity bit providing a check on bits in a preceding token.

Claims

1. A communication interface for use in a communication system interconnecting a computer with at least one other device, said interface comprising:

(a) output circuitry for outputting messages, said output circuitry including control circuitry and encoding circuitry for providing two parallel outputs,

(i) one of said parallel outputs being in the form of an outgoing data signal representing data and including a serial bit pattern forming at least part of an output message, said serial bit pattern providing a sequence of signal transitions between two levels with said transitions occurring only when said data changes, and

(ii) another one of said parallel being in the form of an outgoing strobe signal which, when data is output in the data signal, has signal transitions only at bit boundaries where there is no transition on the data signal, and

(b) input circuitry for inputting messages, said input circuitry including decoding circuitry having a first input to receive an incoming data signal and a second input to receive an incoming strobe signal, said decoding circuitry being arranged to respond both to incoming data and incoming strobe signals to decode data encoded in said incoming data signal.

4. A communication interface according to claim 1 in which said control circuitry is arranged to output data in said data signal in tokens of predetermined bit length.

6. A communication interface according to claim 4 wherein each token includes a flag to indicate the token bit length.

7. A communication interface according to claim 1 in which said control circuitry includes a parity bit generator to generate a parity bit for inclusion in each token.

10. A communication interface according to claim 1 in which the control circuitry is arranged to provide control tokens and data tokens each having a respective predetermined bit length, each data token having a greater bit length than a control token.

11. A communication interface according to claim 1 in which the input circuitry includes delay circuitry connected between each of said two inputs and said decoder and means for varying the delay on one or both of said inputs prior to decoding.

12. A communication interface according to claim 1 in which the output circuitry includes flow control means for generating flow control tokens for outputting to a connected communication interface and said input circuitry includes means responsive to input of a flow control token to control operation of the output circuitry in outputting further data signals.

13. A communication interface according to claim 12 in which said input circuitry includes store means for holding a plurality of data signals and said flow control means is responsive to the contents of said store means.

2. A communication interface for use in a communication system interconnecting a computer with at least one other device, said interface comprising:

(a) output circuitry for outputting messages, said output circuitry including

(i) control circuitry and encoding circuitry for encoding and outputting a succession of encoded serial tokens each including a serial bit string, and

(ii) a parity bit generator responsive to successive bits in an encoded serial token and arranged to generate a parity bit after encoding of each serial token, said parity bit being included in a next serial token to provide a parity check responsive to the bits in the preceding serial token, and

(b) input circuitry for inputting messages, said input circuitry including decoding circuitry for inputting and decoding data in each serial token received and a parity checking circuit to detect a parity bit in each serial token and compare said parity bit with a bit pattern including bits from said preceding serial token.

5. A communication interface according to claim 2 in which the control circuitry is operable to output tokens of more than one predetermined bit length.

3. A communication interface for use in a communication system interconnecting a computer with at least one other device, said interface comprising:

(a) output circuitry for outputting messages, said output circuitry including

(i) control circuitry and encoding circuitry for encoding and outputting a succession of variable bit length tokens each including a serial bit string including at least one parity bit and other bits including at least one bit forming a bit length indicator for the token, and

(ii) a parity bit generator responsive to successive said other bits after a bit length indicator in a first token up to and including a bit length indicator in a second token and arranged to generate a parity bit for inclusion in each token, and

(b) input circuitry for inputting messages, said input circuitry including decoding circuitry for inputting and decoding data in each token received and a parity checking circuit to detect a parity bit in each token and compare said parity bit with a bit pattern after a bit length indicator in one token up to and including the next bit length indicator.

8. A communication interface according to claim 3 in which said control circuitry includes a flag bit generator to generate a flag bit for inclusion in each token to identify each token as a data token or a control token.

9. A communication interface according to claim 8 in which said flag bit provides an indication of the token length.

14. A communication interface according to claim 8 in which said encoding circuitry is arranged to provide said parity bit and said flag bit at the start of each token.

15. A communication interface according to claim 8 in which said parity bit generator is coupled to said encoder so as to respond to the number of bits encoded in a first token after a flag bit in said first token and to supply a parity bit in a first location of a second token indicating an aggregate of said number of bits from said first token together with the parity and flag bits of said second token.

16. A method of effecting communication between at least two interconnected devices, at least one of which devices comprises a computer device, said method comprising the steps of:

(a) establishing parallel data signal and strobe signal communication paths between two link interfaces each connected to a respective one of said devices,

(b) encoding a serial bit pattern to form a data signal representing data as at least part of an output message, said serial bit pattern providing a sequence of signal transitions between two levels with said transitions occurring only when said data changes,

(c) outputting said data signal on the data signal path from one link interface,

(d) outputting on the strobe signal path from the said one link interface a strobe signal which, when data is output in the data signal transitions only at bit boundaries where there is no transition on the data signal, and

(e) inputting said data and strobe signals in parallel at the other link interface and responding to both said data and strobe signals to decode data encoded in said data signal.

21. A method according to claim 16 further comprising establishing four unidirectional communication paths between each pair of link interfaces, said four paths comprising a first parallel pair of data and signal paths in one direction and a second parallel pair of data and signal paths in the opposite direction.

22. A method according to claim 16 wherein data is output by a link interface in tokens of predetermined bit length.

23. A method according to claim 22 wherein data is output by a link interface in tokens of more than one predetermined bit length.

27. A method according to claim 16 wherein messages are transmitted between connected link interfaces in variable length packets, each packet comprising a multiple number of tokens, each token being of a predetermined bit length and providing an end of packet token at the end of each packet.

28. A method according to claim 27 further comprising including an end of message token at the end of a last packet in a message.

29. A method according to claim 16 including providing an alignment token to cause simultaneous transitions in said data and strobe paths when no data is transmitted on the data path and using said simultaneous transitions to effect alignment of the signals on the data and strobe paths when input by a link interface.

30. A method according to claim 16 including forming flow control tokens for outputting by a link interface, outputting data from a first interface to a second interface, outputting a flow control token from said second interface to said first interface to indicate to the first interface that further data tokens may be output to the second interface.

31. A method according to claim 30 further comprising maintaining a count which is adjusted by output of tokens by an outputting link interface, inhibiting further output of data tokens from said link interface when the count reaches a predetermined number and adjusting said count in response to input of a flow control token from a connected interface to permit output of further data tokens.

32. A method according to claims 16 wherein each link interface is arranged to output data tokens of a predetermined bit length longer than a second predetermined bit length for control tokens.

33. A method according to claim 16 wherein each link interface is arranged to output control tokens of two types, a first type for controlling operation of a connected link interface and a second type for use by said device connected to the second link interface.

34. A method according to claim 33 wherein each link interface is arranged in its input circuitry to store data tokens and control tokens of said second type.

35. A method according to claim 34 including transferring data tokens and control tokens of said second type from a store in the link interface to a said device connected to the link interface by use of a synchronised handshake.

36. A method according to claim 16 wherein a link interface is arranged to output a packet which includes in one or more data tokens an address of a communication channel to be used in a said device connected to a link interface arranged to receive said packet.

37. A method according to claim 16 or claim 18 comprising effecting bidirectional communication between a plurality of devices included in a network having a plurality of microcomputers and at least one routing switch.

17. A method of effecting communication between at least two interconnected devices, at least one of which devices comprises a computer device, said method comprising the steps of:

(a) establishing unidirectional communication paths between two link interfaces each connected to a respective one of said devices,

(b) encoding a succession of tokens each including a serial bit string,

(c) generating a parity bit in response to successive bits of a first token,

(d) including said parity bit in the serial bit string of a second token following said first token to provide a check on the number of bits in said first token,

(e) transmitting said first and second tokens serially from one said link interface to the other link interface,

(f) decoding said first and second tokens at said other link interface, and

(g) detecting said parity bit in said second token and comparing said parity bit with the decoded bit pattern.

18. A method of effecting communication between at least two interconnected devices, at least one of which devices comprises a computer device, said method comprising the steps of:

(a) establishing unidirectional communication paths between two link interfaces each connected to a respective one of said devices,

(b) encoding a succession of variable length tokens each including a serial bit string including at least one parity bit and other bits including a token bit length indicator,

(c) generating a parity bit in response to successive bits of a first token following a bit length indicator for said first token up to and including a bit length indicator for a next token,

(d) including said parity bit in the serial bit string of said next token to provide a check on bits in said first token and the bit length indicator of said next token,

(e) transmitting said first and second tokens serially from one said link interface to the other link interface,

(f) decoding said first and next tokens at said other link interface to provide a decoded bit pattern, and

(g) detecting said parity bit and comparing said parity bit with the decoded bit pattern.

19. A method according to claim 18 in the said parity bit is located in said next token.

20. A method according to claim 18 in which each said parity bit forms a first bit in a token and said bit length indicator forms a second bit.

24. A method according to claim 18 further including generating a flag bit for inclusion in each token to identify the token as a data token or a control token.

25. A method according to claim 24 wherein said parity bit and flag bit are located at first and second bit positions respectively in each token.

26. A method according to claim 25 further comprising forming two successive control tokens to form a compound token, the first of said control tokens having a bit pattern indicating that a further token is required to determine a control indicated by the compound token.