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Method of fabricating power VFET gate-refill

  • US 5,342,795 A
  • Filed: 11/15/1993
  • Issued: 08/30/1994
  • Est. Priority Date: 04/30/1992
  • Status: Expired due to Term
First Claim
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1. A method of forming a vertical transistor device comprising:

  • forming a n-type first drain/source layer over a substrate;

    patterning a portion of said first drain/source layer to form a channel and a trench;

    forming a p-type carbon doped gate structure in said trench;

    forming a n-type second drain/source layer over said gate structure and said channel;

    contacting said gate structure;

    forming p-ohmic contact to said gate structure;

    forming n-ohmic source contact; and

    forming n-ohmic drain contact.

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