Method of fabricating power VFET gate-refill
First Claim
Patent Images
1. A method of forming a vertical transistor device comprising:
- forming a n-type first drain/source layer over a substrate;
patterning a portion of said first drain/source layer to form a channel and a trench;
forming a p-type carbon doped gate structure in said trench;
forming a n-type second drain/source layer over said gate structure and said channel;
contacting said gate structure;
forming p-ohmic contact to said gate structure;
forming n-ohmic source contact; and
forming n-ohmic drain contact.
1 Assignment
0 Petitions
Accused Products
Abstract
This is a method of forming a vertical transistor device comprising: forming an n-type first drain/source layer 42; patterning a portion of the first drain/source layer 42 to form a channel 44 and a trench; forming a p-type gate structure 46 in the trench; and forming a n-type second drain/source layer 48 over the gate structure 46 and the channel 44; contacting the gate structure 54; forming p-ohmic contact to the gate structure 56; forming n-ohmic source contact 54; and forming n-ohmic drain contact 58. Other devices and methods are also disclosed.
-
Citations
13 Claims
-
1. A method of forming a vertical transistor device comprising:
-
forming a n-type first drain/source layer over a substrate; patterning a portion of said first drain/source layer to form a channel and a trench; forming a p-type carbon doped gate structure in said trench; forming a n-type second drain/source layer over said gate structure and said channel; contacting said gate structure; forming p-ohmic contact to said gate structure; forming n-ohmic source contact; and forming n-ohmic drain contact. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
-
Specification