Dense vertical programmable read only memory cell structure and processes for making them

• US 5,343,063 A
• Filed: 12/18/1990
• Issued: 08/30/1994
• Est. Priority Date: 12/18/1990
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SunDisk Corporation (Seagate Technology Holdings Plc)
• Inventors: Harari, Eliyahou, Guterman, Daniel C., Yuan, Jack H., Samachisa, Gheorghe
• Primary Examiner(s): NGO, NGAN V
• Application Number:
  US07/629,250
• Time in Patent Office: 1,351 Days
• Field of Search: 357/23.5, 357/23.4, 357/23.11, 357/49, 357/53, 257/316, 257/317, 257/319, 257/320, 257/321, 365/900
• US Class Current: 257/317
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A memory array of PROM, EPROM or EEPROM cells has each cell formed in a trench of a thick oxide layer deposited on a silicon substrate, in a manner that a significant portion of opposing areas of the floating gate and control gate of each cell which provide capacitive coupling between them are formed vertically. This allows the density of the array to be increased since the amount of semiconductor substrate area occupied by each cell is decreased without having to sacrifice the amount or quality of the capacitive coupling. Further, a technique of forming capacitive coupling between the floating gate and an erase gate in a flash EEPROM array cell with improved endurance is disclosed.

Claims

1. In an electrically programmable memory device including an electrically conductive floating gate having a given surface area positioned over at least a portion of a channel region in a substantially planar surface of a semiconductor substrate between source and drain diffusion therein and insulated from the substrate surface by a gate dielectric layer therebetween, and an electrically conductive control gate having a surface area capacitively coupled through a control gate dielectric layer to an opposing surface area of said floating gate, said floating gate being characterized by controlling the amount of conduction in said at least a portion of channel region in proportion to the floating gate electrical potential level, the improvement wherein at least thirty-five percent of the opposing surface areas of said floating and control gates constituting said capacitive coupling are oriented substantially perpendicular to said substrate surface and extend away therefrom in a region of said floating gate given surface area, said floating and control gates being positioned in a trench with the floating gate extending from the gate dielectric along opposing sidewalls of the trench to terminate in edges on the outside of the trench on either side thereof, whereby an amount of area of said substrate that is occupied by said memory device is minimized, and wherein said floating gate given surface area extends over only a portion of the distance between the source and drain diffusions and said control gate extends the rest of the distance therebetween over the channel region with the gate dielectric layer therebetween, whereby said device is a split channel type of memory cell.

2. The improved memory device according to claim 1 wherein said opposing surface areas include a bottom and opposite sidewalls of said control gate.

3. The improved memory device according to claim 1 wherein said floating gate is substantially solid and said opposing surface areas include opposite end surfaces of said floating gate.

4. The improved memory device according to any one of claims 1-3 wherein said trench is formed in an insulation layer carried by said semiconductor substrate surface.

5. In an electrically programmable memory device including an electrically conductive floating gate having a given surface area positioned over at least a portion of a channel region in a substantially planar surface of a semiconductor substrate between source and drain diffusions therein and insulated from the substrate surface by a gate dielectric layer therebetween, and an electrically conductive control gate having a surface area capacitively coupled through a control gate dielectric layer to an opposing surface area of said floating gate, an electrically conductive erase gate that is capacitively coupled with said floating gate through a layer of erase gate dielectric, said floating gate being characterized by controlling the amount of conduction in said at least a portion of channel region in proportion to the floating gate electrical potential level, the improvement wherein at least thirty-five percent of the opposing surface areas of said floating and control gates constituting said capacitive coupling are oriented substantially perpendicular to said substrate surface and extend away therefrom in a region of said floating gate given surface area, whereby an amount of area of said substrate that is occupied by said memory device is minimized, wherein said erase gate is positioned adjacent said substrate surface outside of said channel region and capacitively coupled thereto through an erase gate dielectric layer, thereby to serve as a field plate to electrically isolate said device from other devices on said substrate, and wherein said floating gate given surface area extends over only a portion of the distance between the source and drain diffusions and said control gate extends the rest of the distance therebetween over the channel region with the gate dielectric layer therebetween, whereby said device is a split channel type of memory cell.

36. The improved memory device according to either of claims 5 or 6 wherein said opposing surface areas include a bottom and opposite sidewalls of said control gate.

37. The improved memory device according to either of claims 5 or 6 wherein said floating gate is substantially solid and said opposing surface areas include opposite end surfaces of said floating gate.

38. The improved memory device according to either of claims 5 or 6 wherein said opposing surface areas of said floating and control gates are positioned within a trench, said floating gate extending along opposite sidewalls of the trench and out of the trench.

6. In an electrically programmable memory device including an electrically conductive floating gate having a given surface area positioned over at least a portion of a channel region in a substantially planar surface of a semiconductor substrate between source and drain diffusions therein and insulated from the substrate surface by a gate dielectric layer therebetween, and an electrically conductive control gate having a surface area capacitively coupled through a control gate dielectric layer to an opposing surface area of said floating gate, an electrically conductive erase gate that is capacitively coupled with said floating gate through a layer of erase gate dielectric, said floating gate being characterized by controlling the amount of conduction in at least a portion of channel region in proportion to the floating gate electrical potential level, the improvement wherein at least thirty-five percent of the opposing surface areas of said floating and control gates constituting said capacitive coupling are oriented substantially perpendicular to said substrate surface and extend away therefrom in a region of said floating gate given surface area, whereby an amount of area of said substrate that is occupied by said memory device is minimized, wherein said erase gate is positioned adjacent an edge of said floating gate displaced from said substrate, and wherein said floating gate given surface area extends over only a portion of the distance between the source and drain diffusions and said control gate extends the rest of the distance therebetween over the channel region with the gate dielectric layer therebetween, whereby said device is a split channel type of memory cell.

7. A memory device cell, comprising:

a semiconductor substrate having source and drain diffusions spaced a distance apart in one substantially planar surface thereof,

an isolation dielectric layer carried by said substrate surface,

a trench with opposing sidewalls formed through the isolation dielectric layer to said substrate surface but substantially not into said substrate surface, said trench being oriented with a length extending between said source and drain diffusions, having a width between sidewalls that is substantially perpendicular to said length, and having a depth that is substantially equal to at least one-half the width in the vicinity of said substrate;

a gate dielectric layer carried by said substrate surface within said trench,

an electrically conductive floating gate structure positioned on said gate dielectric layer with the trench in a manner to be capacitively coupled with said substrate for at least a portion of the trench length between the source and drain diffusions, said floating gate extending from the gate dielectric layer along said sidewalls and extending out of the trench to terminate in edges on a side of the isolation dielectric layer that is furthest displaced from the substrate, and

an electrically conductive control gate positioned within said trench and having a surface area thereof separated from a corresponding surface area of said floating gate by a control gate dielectric layer in a manner to provide capacitive coupling between the floating and control gates, at least thirty-five percent of said coupling area occurring in surfaces within said trench that are oriented substantially orthogonal to said substrate surface.

8. The memory device according to claim 7 wherein said surfaces within said trench that are oriented substantially orthogonal to said substrate surface are oriented along the length of the trench.

9. The memory device cell according to claim 7 wherein said surfaces within said trench that are oriented substantially orthogonal to said substrate surface are oriented along the width of the trench.

10. The memory device according to any one of claims 7-9 wherein the isolation dielectric layer is greater than 0.2 microns thick.

33. The memory device cell according to any one of claims 7-9 additionally comprising an electrically conductive erase gate positioned on the side of the isolation dielectric layer that is furthest displaced from the substrate and capacitively coupled with one of said floating gate edges through an erase gate dielectric layer.

11. A memory device cell, comprising:

a semiconductor substrate having source and drain diffusions spaced a distance apart in one substantially planar surface thereof,

an isolation dielectric layer carried by said substrate surface,

a trench formed through the isolation dielectric layer to said substrate surface but substantially not into said substrate surface, said trench being oriented with a length extending between said source and drain diffusions, having a width substantially perpendicular to said length, and having a depth that is substantially equal to at least one-half the width in the vicinity of said substrate,

a gate dielectric layer carried by said substrate surface within said trench,

an electrically conductive floating gate structure positioned on said gate dielectric layer within the trench in a manner to be capacitively coupled with said substrate for at least a portion of the trench length between the source and drain diffusions,

an electrically conductive control gate positioned within said trench and having a surface area thereof separated from a corresponding surface area of said floating gate by a control gate dielectric layer in a manner to provide capacitive coupling between the floating and control gates, at least thirty-five percent of said coupling area occurring in surfaces within said trench that are oriented substantially orthogonal to said substrate surface, and

an electrically conductive erase gate capacitively coupled with the floating gate through an erase gate dielectric layer adjacent a surface of the isolation dielectric that is substantially parallel with and furthest displaced from said substrate surface.

14. The memory device cell according to any one of claims 7, 11, 12 or 13 wherein said floating gate extends only a portion of the trench length between the source and drain diffusions, said control gate extending a remaining distance along the trench length between the source and drain diffusions and over said gate dielectric layer, whereby a split channel memory device cell is formed.

39. The memory device cell according to any one of claims 11-13 wherein said surfaces within said trench that are oriented substantially orthogonal to said substrate surface are oriented along the length of the trench.

40. The memory device cell according to any one of claims 11-13 wherein said surfaces within said trench that are oriented substantially orthogonal to said substrate surface are oriented along the width of the trench.

41. The memory device cell according to any one of claims 11-13 wherein the isolation dielectric layer is greater than 0.2 microns thick.

12. A memory device cell, comprising:

a semiconductor substrate having source and drain diffusions spaced a distance apart in one substantially planar surface thereof,

an isolation dielectric layer carried by said substrate surface,

a trench formed through the isolation dielectric layer to said substrate surface but substantially not into said substrate surface, said trench being oriented with a length extending between said source and drain diffusions, having a width substantially perpendicular to said length, and having a depth that is substantially equal to at least one-half the width in the vicinity of said substrate,

a gate dielectric layer carried by said substrate surface within said trench,

an electrically conductive floating gate structure positioned on said gate dielectric layer within the trench in a manner to be capacitively coupled with said substrate for at least a portion of the trench length between the source and drain diffusions,

an electrically conductive control gate positioned within said trench and having a surface area thereof separated from a corresponding surface area of said floating gate by a control gate dielectric layer in a manner to provide capacitive coupling between the floating and control gates, at least thirty-five percent of said coupling area occurring in surfaces within said trench that are oriented substantially orthogonal to said substrate surface, and

an electrically conductive erase gate buried within the isolation dielectric layer and separated from the substrate surface by a gate dielectric layer in a manner to be capacitively coupled with the substrate therethrough, said erase gate additionally being positioned adjacent the floating gate with an erase gate dielectric layer therebetween.

13. A memory device cell, comprising:

a semiconductor substrate having source and drain diffusions spaced a distance apart in one substantially planar surface thereof,

an isolation dielectric layer carried by said substrate surface,

a trench formed through the isolation dielectric layer to said substrate surface but substantially not into said substrate surface, said trench being oriented with a length extending between said source and drain diffusions, having a width substantially perpendicular to said length, and having a depth that is substantially equal to at least one-half the width in the vicinity of said substrate,

a gate dielectric layer carried by said substrate surface within said trench,

an electrically conductive floating gate structure positioned on said gate dielectric layer within the trench in a manner to be capacitively coupled with said substrate for at least a portion of the trench length between the source and drain diffusions,

an electrically conductive control gate positioned within said trench and having a surface area thereof separated from a corresponding surface area of said floating gate by a control gate dielectric layer in a manner to provide capacitive coupling between the floating and control gates, at least thirty-five percent of said coupling area occurring in surfaces within said trench that are oriented substantially orthogonal to said substrate surface, and

an electrically conductive erase gate positioned within said isolation dielectric layer adjacent said trench and having an edge thereof separated from the floating gate by a layer of erase gate dielectric.

15. An array of a plurality of memory device cells, comprising:

a semiconductor substrate having a substantially planar surface,

a plurality of spaced apart, substantially parallel and elongated source and drain diffusions formed in said substrate surface with their lengths extending in a first direction across the substrate,

a layer of isolation dielectric covering said substrate surface and having a plurality of spaced apart, substantially parallel and elongated trenches therethrough to said substrate surface but substantially without extending into said substrate surface, said trenches oriented with their lengths extending in a second direction across the substrate, said first and second directions being substantially orthogonal to each other,

a layer of gate dielectric on said substrate surface within the trenches,

a plurality of floating gates formed in said trenches on said gate dielectric layer and spaced apart along the length of the trenches with one floating gate positioned between adjacent source and drain diffusions in a manner to be capacitively coupled to a substrate surface channel region therebetween, said floating gates extending from the gate dielectric layer of their respective trenches and extending out of the trench to terminate on either side thereof in edges positioned on a surface of the isolation dielectric layer furthest displaced from the substrate, and

a control gate positioned at least partially in each of said plurality of trenches and extending along its length past at least several floating gates therein in a manner to form areas of capacitive coupling between the control gate and each of said at least several floating gates through a control gate dielectric layer, at least thirty-five percent of said areas of capacitive coupling being oriented substantially orthogonally to said substrate surface and within the trench.

16. The memory device cell array according to claim 15 wherein the floating gates are formed over said substrate and with walls positioned against opposing trench sidewalls areas in a manner to form a space between said floating gate walls through which said control gate passes.

17. The memory device cell array according to claim 15 wherein the floating gates are substantially solid between opposing trench sidewall areas and wherein said areas of capacitive coupling include opposing floating gate ends along the length of the trench.

22. The memory device cell array according to any one of claims 15-21 wherein said isolation dielectric layer has a thickness that is equal to or greater than a width of the floating gates adjacent the gate dielectric layer.

24. The memory device cell array according to any one of claims 15-23 wherein the floating gates extend only a portion of the distance between adjacent source and drain diffusions along the length of the trenches and the control gate is capacitively coupled to the substrate through the gate dielectric for a remaining distance between adjacent source and drain diffusions, whereby an array of split-channel memory devices is formed.

34. The memory device cell array according to any one of claims 15-17 additionally comprising a plurality of spaced apart, substantially parallel and elongated erase gates with their lengths extending in said second direction and positioned across the surface of said isolation dielectric layer furthest displaced from the substrate in a manner to provide a capacitive coupling with said floating gate edges through an erase gate dielectric layer.

35. The memory device cell array according to any one of claims 15-17 wherein the layer of isolation dielectric extends substantially completely between said plurality of trenches.

18. An array of a plurality of memory device cells, comprising:

a semiconductor substrate having a substantially planar surface,

a plurality of spaced apart, substantially parallel and elongated source and drain diffusions formed in said substrate surface with their lengths extending in a first direction across the substrate,

a layer of isolation dielectric covering said substrate surface and having a plurality of spaced apart, substantially parallel and elongated trenches therethrough to said substrate surface but substantially without extending into said substrate surface, said trenches oriented with their lengths extending in a second direction across the substrate, said first and second directions being substantially orthogonal to each other,

a layer of gate dielectric on said substrate surface within the trenches,

a plurality of floating gates formed in said trenches on said gate dielectric layer and spaced apart along the length of the trenches with one floating gate positioned between adjacent source and drain diffusions in a manner to be capacitively coupled to a substrate surface channel region therebetween,

a control gate positioned at least partially in each of said plurality of trenches and extending along its length past at least several floating gates therein in a manner to form areas of capacitive coupling between the control gate and each of said at least several floating gates through a control gate dielectric layer, at least thirty-five percent of said areas of capacitive coupling being oriented substantially orthogonally to said substrate surface and within the trench, and

a plurality of spaced apart, substantially parallel and elongated erase gates with their lengths extending in said second direction and positioned atop said isolation dielectric layer with a capacitive coupling with a top edge of said floating gate through an erase gate dielectric layer.

42. The memory device cell array according to any one of claims 18, 20, 21 and 23 wherein the floating gates are formed over said substrate and with walls positioned against opposing trench sidewall areas in a manner to form a space between said floating gate walls through which said control gate passes.

43. The memory device cell array according to any one of claims 18, 20, 21 and 23 wherein the floating gates are substantially solid between opposing trench sidewall areas and wherein said areas of capacitive coupling include opposing floating gate ends along the length of the trench.

19. An array of a plurality of memory device cells, comprising:

a semiconductor substrate having a substantially planar surface,

a plurality of spaced apart, substantially parallel and elongated source and drain diffusions formed in said substrate surface with their lengths extending in a first direction across the substrate,

a layer of isolation dielectric covering said substrate surface and having a plurality of spaced apart, substantially parallel and elongated trenches therethrough to said substrate surface but substantially without extending into said substrate surface, said trenches oriented with their lengths extending in a second direction across the substrate, said first and second directions being substantially orthogonal to each other,

a layer of gate dielectric on said substrate surface within the trenches,

a plurality of floating gates formed in said trenches on said gate dielectric layer and spaced apart along the length of the trenches with one floating gate positioned between adjacent source and drain diffusions in a manner to be capacitively coupled to a substrate surface channel region therebetween,

a control gate positioned at least partially in each of said plurality of trenches and extending along its length past at least several floating gates therein in a manner to form areas of capacitive coupling between the control gate and each of said at least several floating gates through a control gate dielectric layer, at least thirty-five percent of said areas of capacitive coupling being oriented substantially orthogonally to said substrate surface and within the trench,

wherein the portions of the floating gates formed against opposing trench sidewalls extend further away from said substrate than said control gate, and

an erase gate formed atop said isolation dielectric and extending substantially continuously over an area including a plurality of floating gates in one or more trenches.

20. An array of a plurality of memory device cells, comprising:

a semiconductor substrate having a substantially planar surface,

a plurality of spaced apart, substantially parallel and elongated source and drain diffusions formed in said substrate surface with their lengths extending in a first direction across the substrate,

a layer of isolation dielectric covering said substrate surface and having a plurality of spaced apart, substantially parallel and elongated trenches therethrough to said substrate surface but substantially without extending into said substrate surface, said trenches oriented with their lengths extending in a second direction across the substrate, said first and second directions being substantially orthogonal to each other,

a layer of gate dielectric on said substrate surface within the trenches,

a plurality of floating gates formed in said trenches on said gate dielectric layer and spaced apart along the length of the trenches with one floating gate positioned between adjacent source and drain diffusions in a manner to be capacitively coupled to a substrate surface channel region therebetween,

a control gate positioned at least partially in each of said plurality of trenches and extending along its length past at least several floating gates therein in a manner to form areas of capacitive coupling between the control gate and each of said at least several floating gates through a control gate dielectric layer, at least thirty-five percent of said areas of capacitive coupling being oriented substantially orthogonally to said substrate surface and within the trench, and

a plurality of spaced apart, substantially parallel and elongated erase gates with their lengths extending in said second direction and positioned within said isolation dielectric layer between trenches in a manner to be capacitively coupled through an erase gate dielectric with the floating gates in trenches on opposite sides thereof and capacitively coupled with the substrate through a gate dielectric layer, thereby to provide field plate isolation of the devices in said second direction.

21. An array of a plurality of memory device cells, comprising:

a semiconductor substrate having a substantially planar surface,

a plurality of spaced apart, substantially parallel and elongated source and drain diffusions formed in said substrate surface with their lengths extending in a first direction across the substrate,

a layer of isolation dielectric covering said substrate surface and having a plurality of spaced apart, substantially parallel and elongated trenches therethrough to said substrate surface but substantially without extending into said substrate surface, said trenches oriented with their lengths extending in a second direction across the substrate, said first and second directions being substantially orthogonal to each other,

a layer of gate dielectric on said substrate surface within the trenches,

a plurality of floating gates formed in said trenches on said gate dielectric layer and spaced apart along the length of the trenches with one floating gate positioned between adjacent source and drain diffusions in a manner to be capacitively coupled to a substrate surface channel region therebetween,

a control gate positioned at least partially in each of said plurality of trenches and extending along its length past at least several floating gates therein in a manner to form areas of capacitive coupling between the control gate and each of said at least several floating gates through a control gate dielectric layer, at least thirty-five percent of said areas of capacitive coupling being oriented substantially orthogonally to said substrate surface and within the trench, and

a plurality of spaced apart, substantially parallel and elongated electrically conductive erase gates with their lengths extending in said second direction and positioned between said trenches with sidewall edges thereof being capacitively coupled to a sidewall of said floating gate through an erase gate dielectric layer therebetween.

23. An array of a plurality of memory device cells, comprising:

a semiconductor substrate having a substantially planar surface,

a plurality of spaced apart, substantially parallel and elongated source and drain diffusions formed in said substrate surface with their lengths extending in a first direction across the substrate,

a layer of isolation dielectric covering said substrate surface and having a plurality of spaced apart, substantially parallel and elongated trenches therethrough to said substrate surface but substantially without extending into said substrate surface, said trenches oriented with their lengths extending in a second direction across the substrate, said first and second directions being substantially orthogonal to each other,

a layer of gate dielectric on said substrate surface within the trenches,

a plurality of floating gates formed in said trenches on said gate dielectric layer and spaced apart along the length of the trenches with one floating gate positioned between adjacent source and drain diffusions in a manner to be capacitively coupled to a substrate surface channel region therebetween,

a control gate positioned at least partially in each of said plurality of trenches and extending along its length past at least several floating gates therein in a manner to form areas of capacitive coupling between the control gate and each of said at least several floating gates through a control gate dielectric layer, at least thirty-five percent of said areas of capacitive coupling being oriented substantially orthogonally to said substrate surface and within the trench, and

wherein the trenches in the isolation dielectric layer include spacers formed on opposite sidewalls in a manner to gradually slope the sidewalls inward toward each other as they get closer to the substrate, thereby narrowing an effective width of the channel regions.

25. In an electrically programmable memory device including an electrically conductive floating gate having a given surface area positioned over at least a portion of a channel region in a substantially planar surface of a semiconductor substrate between source and drain diffusions therein and insulated from the substrate surface by a gate dielectric layer therebetween, an electrically conductive control gate having a surface area capacitively coupled through a control gate dielectric layer to an opposing surface area of said floating gate, said floating gate being characterized by controlling the amount of conduction in said at least a portion of channel region in proportion to the floating gate electric potential level, and an electrically conductive erase gate that is capacitively coupled with said floating gate through a layer of erase gate dielectric, the improvements wherein at least thirty-five percent of the opposing surface areas of said floating and control gates constituting said capacitive coupling are oriented substantially perpendicular to said substrate surface and extend away therefrom in a region of said floating gate given surface area, whereby an amount of area of said substrate that is occupied by said memory device is minimized, and wherein the erase gate is positioned adjacent an edge of said floating gate displaced from said substrate.

26. The improved memory device according to claim 25 wherein the control gate extends through at least a portion of the floating gate, said opposing surface areas including a bottom and opposite sidewalls of said control gate.

27. The improved memory device according to claim 25 wherein said floating gate is substantially solid and said opposing surface areas include opposite end surfaces of said floating gate.

28. The improved memory device according to any one of claims 25-27 wherein said opposing surface areas of said floating and control gates are positioned within a trench formed in an insulation layer carried by said semiconductor substrate surface.

29. In an electrically programmable memory device including an electrically conductive floating gate having a given surface area positioned over at least a portion of a channel region in a substantially planar surface of a semiconductor substrate between source and drain diffusions therein and insulated from the substrate surface by a gate dielectric layer therebetween, an electrically conductive control gate having a surface area capacitively coupled through a dielectric layer to an opposing surface area of said floating gate, said floating gate being characterized by controlling the amount of conduction in said at least a portion of channel region in proportion to the floating gate electrical potential level, and an electrically conductive erase gate that is capacitively coupled with said floating gate through a layer of erase dielectric, the improvements wherein at least thirty-five percent of the opposing surface areas of said floating and control gates constituting said capacitive coupling are oriented substantially perpendicular to said substrate surface and extend away therefrom in a region of said floating gate given surface area, whereby an amount of area of said substrate that is occupied by said memory device is minimized, and wherein said erase gate is positioned adjacent said substrate surface outside of said channel region and capacitively coupled thereto through a dielectric layer, thereby to serve as a field plate to electrically isolate said device from other devices on said substrate.

30. The improved memory device according to claim 29 wherein said opposing surface areas include a bottom and opposite sidewalls of said control gate.

31. The improved memory device according to claim 29 wherein said floating gate is substantially solid and said opposing surface areas include opposite end surfaces of said floating gate.

32. The improved memory device according to any one of claims 29-31 wherein said opposing surface areas of said floating and control gates are positioned within a trench formed in an insulation layer carried by said semiconductor substrate surface.