Semiconductor device and method of manufacturing same
First Claim
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1. A semiconductor device, comprising:
- a thin film transistor formed by a gate insulator film stacked on a first gate electrode layer and a semiconductor layer stacked on the gate insulator film;
a portion of said semiconductor layer being electrically connected by a conductive layer to a second gate electrode layer through a contact hole formed in said gate insulator layer; and
an insulator layer inserted between a portion of said conductive layer and said semiconductor layer; and
said thin film transistor comprising a load transistor of a SRAM memory cell, one end of said semiconductor layer merging into a power supply line connected to said load transistor, and an additional conductive layer portion arranged over said power supply line comprising a shunt line of the power supply line.
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Abstract
In a semiconductor device having a thin film transistor in which a gate insulator film and a semiconductor layer are formed on a gate electrode layer, and a portion of the semiconductor layer is connected to a specific gate electrode layer through a contact hole formed in the gate insulator film, a static random access memory is constituted by memory cells in each of which a conductive layer stacked on the upper layer side of the semiconductor layer through an insulator layer is inserted in the contact hole formed in the gate insulator film, and the portion of the semiconductor layer is electrically connected to the specific gate electrode layer through the conductive layer.
79 Citations
1 Claim
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1. A semiconductor device, comprising:
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a thin film transistor formed by a gate insulator film stacked on a first gate electrode layer and a semiconductor layer stacked on the gate insulator film; a portion of said semiconductor layer being electrically connected by a conductive layer to a second gate electrode layer through a contact hole formed in said gate insulator layer; and an insulator layer inserted between a portion of said conductive layer and said semiconductor layer; and said thin film transistor comprising a load transistor of a SRAM memory cell, one end of said semiconductor layer merging into a power supply line connected to said load transistor, and an additional conductive layer portion arranged over said power supply line comprising a shunt line of the power supply line.
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Specification
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Current AssigneeSony Corporation (Sony Group Corp.)
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Original AssigneeSony Corporation (Sony Group Corp.)
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InventorsShinguu, Masataka, Yamada, Makoto, Okamoto, Yutaka
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Primary Examiner(s)Prenty, Mark V.
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Application NumberUS08/033,369Time in Patent Office530 DaysField of Search257/393, 257/66, 257/365, 257/366, 257/379, 257/532, 257/773, 257/776, 257/903, 257/904US Class Current257/393CPC Class CodesH10B 10/125 the MOSFET being a thin fil...Y10S 257/903 FET configuration adapted f...
