Analog/digital hybrid masterslice IC

• US 5,343,083 A
• Filed: 02/03/1993
• Issued: 08/30/1994
• Est. Priority Date: 02/03/1992
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Fuse, Mamoru
• Primary Examiner(s): Mullins, James B.
• Assistant Examiner(s): DUDEK, JAMES A
• Application Number:
  US08/012,736
• Time in Patent Office: 573 Days
• Field of Search: 307/242, 307/570, 307/490, 307/498, 307/499, 307/231, 307/465, 307/475, 364/600, 364/602
• US Class Current: 327/404
• CPC Class Codes: H01L 27/0203 Particular design considerations for integrated circuits
• CPC Class Codes: H03K 17/567 Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/356017 using additional transistors in the input circuit H03K3/356104, H03K3/3562 take precedence
• CPC Class Codes: H03K 3/356113 using additional transistors in the input circuit

Abstract

An analog/digital hybrid masterslice IC includes an analog circuit section formed by a CMOS analog section and an analog master section in which a plurality of basic blocks are arranged in array form, and a digital circuit section formed by a gate array section. The digital circuit section operates under a power source voltage lower than that supplied to the analog circuit section. The IC further includes a selector circuit disposed between the digital circuit section and the analog circuit section, for testing the analog circuit section and the digital circuit section independently from each other, and a level shift circuit disposed between the selector circuit and the analog master section, for amplifying an output level from the gate array section. The level shift circuit is fixedly built-in in a masterwafer substrate as a hard-macro. The arrangement ensures that there is no possibility of any digital noise entering the analog circuit.

Claims

1. An analog/digital hybrid masterslice IC comprising:

an analog master section in which basic blocks each having a cell formed by a bipolar device and having a MOS transistor connected to said cell are arranged in array form;

an analog section which, together with said analog master section, constitutes an analog circuit section;

a digital logic circuit section which operates under a power source voltage lower than that supplied to said analog circuit section;

a selector circuit which is disposed between said digital logic circuit section and said analog circuit section and operates for testing said analog circuit section and said digital logic circuit section independently from each other; and

a level shift circuit which amplifies a level of an output signal from said digital logic circuit section, said level shift circuit being disposed between said selector circuit and said analog circuit section and fixedly built-in in a masterwafer substrate as a hard-macro.

2. An analog/digital hybrid masterslice IC according to claim 1, in which said level shift circuit is one which converts a digital signal of 5 V_P-P to that of a higher level.

3. An analog/digital hybrid masterslice IC according to claim 1, in which said analog section is formed by a CMOS device.

4. An analog/digital hybrid masterslice IC according to claim 1, in which said digital logic circuit section is formed by a gate array.

5. An analog/digital hybrid masterslice IC according to claim 1, in which said level shift circuit includes:

a first, a second and a third power supply terminal;

a first P-channel MOS transistor having a drain, a source connected to said first power supply terminal, and a gate connected to an input terminal;

a first N-channel MOS transistor having a drain connected to the drain of said first P-channel MOS transistor, a source connected to said second power supply terminal, and a gate connected to said input terminal, said first N-channel MOS transistor together with said first P-channel MOS transistor constituting an inverter;

a second P-channel MOS transistor having a drain, a source connected to said first power supply terminal, and a gate connected to said input terminal;

a third P-channel MOS transistor having a source connected to said first power supply terminal, a gate connected to the drains of said first P-channel MOS transistor and first N-channel MOS transistor, and a drain connected to an output terminal;

a second N-channel MOS transistor having a drain connected to the drain of said second P-channel MOS transistor, a gate connected to the drain of said third P-channel MOS transistor, and a source connected to said third power supply terminal; and

a third N-channel MOS transistor having a drain connected to the drain of said third P-channel MOS transistor, a gate connected to the drain of said second P-channel MOS transistor, and a source connected to said third power supply terminal.