Charge pump circuit for a substrate voltage generator of a semiconductor memory device

• US 5,343,088 A
• Filed: 03/30/1993
• Issued: 08/30/1994
• Est. Priority Date: 03/30/1992
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jeon, Jun-Young
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): LAM, TUAN THIEU
• Application Number:
  US08/038,097
• Time in Patent Office: 518 Days
• Field of Search: 307/296.2, 307/296.4, 307/296.5, 307/296.8
• US Class Current: 327/536
• CPC Class Codes: G05F 3/205 Substrate bias-voltage generators for static stores G11C5/146
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: H02M 3/073 Charge pumps of the Schenkel-type

Abstract

A charge pump circuit for a substrate voltage bias generator. The charge pump circuit generates a negative substrate bias voltage to a semiconductor substrate by performing a charge pumping operation twice during a clock cycle. Additional pumping capacitors are provided to prevent discharging of the substrate bias voltage to ground during transistor switching operations. The transistor switching provides the necessary charge pumping operations within the charge pumping circuit. This circuit provides increased charge pump efficiency and lower stand-by current than conventional charge pump circuits.

Claims

1. A charge pump circuit in a substrate bias voltage generator for pumping a bias charge to a voltage output terminal twice during a complete clock cycle so as to maintain a substantially constant negative voltage level thereto, said charge pump circuit comprising:

first and second pump capacitors for respectively receiving first and second in-phase rectangular wave signals, of different pulse width from one another, at a respective end thereof;

third and fourth pump capacitors for respectively receiving in-phase third and fourth rectangular wave signals, of different pulse width from one another, at a respective end thereof;

a first transistor having a channel connected between a first pumping node and the voltage output terminal, and a control terminal connected to said first pump capacitor, said first pumping node being electrically coupled to said second pumping capacitor;

a second transistor connected between said first pumping node and a ground voltage terminal;

a third transistor having its channel connected between a second pumping node and said voltage output terminal, and a control terminal connected to said fourth pump capacitor, said second pumping node being electrically coupled to said third pumping capacitor;

a fourth transistor connected between said second pumping node and said ground voltage terminal;

first means connected to said first pump capacitor and to said fourth pump capacitor for electrically isolating said first pumping node from said second pumping node;

second means connected to a control terminal of said second transistor and to a control terminal of said fourth transistor for controlling the operation of said second and fourth transistors; and

third means connected to said first and second pumping nodes and to said control terminal of said second transistor and to said control terminal of said fourth transistor, for complementarily operating said second and fourth transistors in response to a signal from said second means.

2. The charge pump circuit of claim 1, wherein said first means comprises:

a fifth transistor having both terminals connected between said first pump capacitor and said first pumping node and a control terminal connected to said fourth pump capacitor; and

a sixth transistor having both terminals connected between said fourth pump capacitor and said second pumping node and a control terminal connected to said first pump capacitor.

3. The charge pump circuit of claim 1, wherein said second means comprises:

a fifth pump capacitor connected to a control terminal of said second transistor for receiving said third rectangular wave signal; and

a sixth pump capacitor connected to a control terminal of said fourth transistor for receiving said second rectangular wave signal.

4. The charge pump circuit of claim 1, wherein said third means comprises:

a seventh transistor having its channel connected between said fifth pump capacitor and said second pumping node, and a control terminal connected to said sixth pump capacitor; and

an eighth transistor having its channel connected between said sixth pump capacitor and said first pumping node, and a control terminal connected to said fifth pump capacitor.

5. The charge pump circuit of claim 1, wherein said first to fourth pump capacitors comprise a P-channel MOS transistor.

6. The charge pump circuit of claim 3, wherein said first to sixth pump capacitors comprise a P-channel MOS transistor.

7. The charge pump circuit of claim 1, wherein said first to fourth transistors comprise a P-channel MOS transistor.

8. The charge pump circuit of claim 2, wherein said first to sixth transistors comprise a P-channel MOS transistor.

9. The charge pump circuit of claim 4, wherein said first to eighth transistors comprise a P-channel MOS transistor.

10. A charge pump circuit in a substrate bias voltage generator for pumping a bias charge to a voltage output terminal twice during a complete clock cycle so as to maintain a substantially constant negative voltage level thereto, said charge pump circuit comprising:

capacitive means for generating first, second, third, and fourth source signals in response to a plurality of different pulse clock signals;

a first transistor having a channel connected between a first pumping node and the voltage output terminal, and a control terminal connected to said first source signal, said first pumping node being electrically coupled to said second source signal;

a second transistor connected between said first pumping node and a ground voltage terminal;

a third transistor having its channel connected between a second pumping node and said voltage output terminal, and a control terminal connected to said fourth source signal, said second pumping node being electrically coupled to said third source signal;

a fourth transistor connected between said second pumping node and said ground voltage terminal;

first means connected to said first source signal and to said fourth source signal for electrically isolating said first pumping node from said second pumping node;

second means connected to a control terminal of said second transistor and a control terminal of said fourth transistor for controlling the operation of said second and fourth transistors; and

third means connected to said first and second pumping nodes and to said control terminal of said second transistor and said control terminal of said fourth transistor, for complementarily operating said second and fourth transistors in response to a signal from said second means.

11. The charge pump circuit of claim 10, wherein said first means comprises:

a fifth transistor having both terminals connected between said first source signal and said first pumping node and a control terminal connected to said fourth source signal; and

a sixth transistor having both terminals connected between said fourth source signal and said second pumping node and a control terminal connected to said first source signal.

12. The charge pump circuit of claim 10, wherein said capacitive means is connected to a driver circuit responsive to a clock signal for generating:

first and second in-phase rectangular wave signals of different pulse width from one another; and

third and fourth rectangular wave signals of different pulse width from one another and of opposite phase from said first and second rectangular waves,

said capacitive means being responsive to each of said first, second, third and fourth rectangular signals for generating said first source signal, said second source signal, said third source signal and said fourth source signal, respectively.