Fully balanced transimpedance amplifier with low noise and wide bandwidth

• US 5,343,160 A
• Filed: 10/21/1992
• Issued: 08/30/1994
• Est. Priority Date: 10/21/1992
• Status: Expired due to Fees

• Current Assignee: TriQuint Semiconductor Incorporated (Qorvo, Inc.)
• Original Assignee: TriQuint Semiconductor Incorporated (Qorvo, Inc.)
• Inventors: Taylor, Stewart S.
• Primary Examiner(s): MOTTOLA, STEVEN J
• Application Number:
  US07/964,173
• Time in Patent Office: 678 Days
• Field of Search: 330/9, 330/124 R, 330/129, 330/253, 330/282, 330/295, 330/308
• US Class Current: 330/9
• CPC Class Codes: H03F 3/087 with IC amplifier blocks H03F3/085 takes precedence

Abstract

A circuit is provided that solves the problem of implementing a fully balanced (differential) transimpedance amplifier with low-noise and wide bandwidth. This is accomplished by direct coupling the feedback resistors from the outputs of the amplifier to the inputs without the use of a blocking capacitor. The low frequency response is thereby improved and the problems created by a DC bias resistor that degrades the noise performance and, in some case, restricts the dynamic range (caused by pulse width distortion for large signals) are eliminated. The amplifier achieves higher voltage gain than prior designs and also results in lower noise and wider bandwidth. The differential nature of the amplifier provides good power supply rejection. While the preferred embodiment is particularly well-suited to GaAs MESFET technology, the invention can also be applied to silicon bipolar and MOS technology.

Claims

1. A balanced transimpedance amplifier circuit comprising:

a first amplifier circuit for amplifying a first signal at a first input line;

a second amplifier circuit for amplifying a second signal at a second input line;

a first capacitor coupled between said first input line and an input node of said first amplifier circuit;

a second capacitor coupled between said second input line and an input node of said second amplifier circuit;

a first feedback network coupled between an output line of said first amplifier circuit and said first input line;

a second feedback network coupled between an output line of said second amplifier circuit and said second input line;

a first voltage offset means coupled in series with said first feedback network; and

a second voltage offset means coupled in series with said second feedback network.

2. The balanced transimpedance amplifier circuit as recited in claim 1 further comprising:

a first automatic gain control circuit coupled to said first amplifier circuit; and

a second automatic gain control circuit coupled to said second amplifier circuit.

3. The balanced transimpedance amplifier circuit as recited in claim 1 further comprising:

a first automatic gain control circuit coupled to said first feedback network; and

a second automatic gain control circuit coupled to said second feedback network.

4. The balanced transimpedance amplifier circuit as recited in claim 2 wherein said first automatic gain control circuit includes a variable impedance device.

5. The balanced transimpedance amplifier circuit as recited in claim 3 wherein said first automatic gain control circuit includes a variable impedance device.

6. The balanced transimpedance amplifier circuit as recited in claim 4 wherein said variable impedance device includes first and second diodes coupled in parallel.

7. The balanced transimpedance amplifier circuit as recited in claim 5 wherein said variable impedance device includes first and second diodes coupled in parallel.

8. The balanced transimpedance amplifier circuit as recited in claim 4 wherein said variable impedance device includes a transistor.

9. The balanced transimpedance amplifier circuit as recited in claim 5 wherein said variable impedance device includes a transistor.

10. The balanced transimpedance amplifier circuit as recited in claim 2 wherein said first automatic gain control circuit is coupled to an input node of said first amplifier circuit.

11. The balanced transimpedance amplifier circuit as recited in claim 3 wherein said first automatic gain control circuit is connected in parallel with said first feedback network.

12. The balanced transimpedance amplifier circuit as recited in claim 1 further comprising a photodetector coupled to said first and second input lines.

13. The balanced transimpedance amplifier circuit as recited in claim 12 wherein said photodetector is a metal-semiconductor-metal detector.

14. The balanced transimpedance amplifier circuit as recited in claim 13 wherein said photodetector and said first and second amplifier circuits are fabricated on a single gallium arsenide integrated circuit chip.

15. The balanced transimpedance amplifier circuit as recited in claim 1 wherein said first and second amplifier circuits are single-ended amplifiers.

16. The balanced transimpedance amplifier circuit as recited in claim 1 wherein said first amplifier circuit is biased with a DC common-mode feedback loop.

17. The balanced transimpedance amplifier circuit as recited in claim 1 wherein said first amplifier circuit includes a transistor having a control terminal coupled to said first capacitor and a second terminal connected to a first power supply terminal.

18. The balanced transimpedance amplifier circuit as recited in claim 17 further comprising a load resistor connected between a third terminal of said transistor and a second power supply terminal.

19. The balanced transimpedance amplifier circuit as recited in claim 18 wherein said transistor is a field-effect transistor.

20. The balanced transimpedance amplifier circuit as recited in claim 18 wherein a voltage drop across said transistor summed with a voltage drop across said load resistor equals a difference in the voltage levels between said first and second power supply terminals.

21. The balanced transimpedance amplifier circuit as recited in claim 1 wherein said first voltage offset means is connected to the output line of said first amplifier circuit and to said first feedback network, and wherein said second voltage offset means is connected to the output line of said second amplifier circuit and to said second feedback network.

22. A balanced transimpedance amplifier circuit comprising:

a first amplifier stage including a first amplifier circuit for amplifying a first signal at a first input line and a second amplifier circuit for amplifying a second signal at a second input line;

a second amplifier stage including a differential amplifier circuit having a first input node coupled to an output node of said first amplifier circuit and having a second input node coupled to an output node of said second amplifier circuit;

a first capacitor coupled between said first input line and an input node of said first amplifier circuit;

a second capacitor coupled between said second input line and an input node of said second amplifier circuit;

a first feedback network coupled between a first output line of said differential amplifier circuit and said first input line;

a second feedback network coupled between a second output line of said differential amplifier circuit and said second input line;

a first voltage offset means coupled in series with said first feedback network; and

a second voltage offset means coupled in series with said second feedback network.

23. The balanced transimpedance amplifier circuit as recited in claim 22 further comprising:

a first automatic gain control circuit coupled to said first amplifier circuit; and

a second automatic gain control circuit coupled to said second amplifier circuit.

24. The balanced transimpedance amplifier circuit as recited in claim 22 further comprising:

a first automatic gain control circuit coupled to said first feedback network; and

a second automatic gain control circuit coupled to said second feedback network.

25. The balanced transimpedance amplifier circuit as recited in claim 23 wherein said first automatic gain control circuit includes a variable impedance device.

26. The balanced transimpedance amplifier circuit as recited in claim 24 wherein said first automatic gain control circuit includes a variable impedance device.

27. The balanced transimpedance amplifier circuit as recited in claim 25 wherein said variable impedance device includes first and second diodes coupled in parallel.

28. The balanced transimpedance amplifier circuit as recited in claim 26 wherein said variable impedance device includes first and second diodes coupled in parallel.

29. The balanced transimpedance amplifier circuit as recited in claim 25 wherein said variable impedance device includes a transistor.

30. The balanced transimpedance amplifier circuit as recited in claim 26 wherein said variable impedance device includes a transistor.

31. The balanced transimpedance amplifier circuit as recited in claim 22 further comprising a photodetector coupled to said first and second input lines.

32. The balanced transimpedance amplifier circuit as recited in claim 31 wherein said photodetector is a metal-semiconductor-metal detector.

33. The balanced transimpedance amplifier circuit as recited in claim 32 wherein said photodetector and said first and second amplifier circuits are fabricated on a single gallium arsenide integrated circuit chip.

34. The balanced transimpedance amplifier circuit as recited in claim 22 wherein said first and second amplifier circuits are single-ended amplifiers.

35. The balanced transimpedance amplifier circuit as recited in claim 22 wherein said first input node of said differential amplifier circuit is a non-inverting input terminal and wherein said second input node of said differential amplifier circuit is an inverting input terminal.

36. The balanced transimpedance amplifier circuit as recited in claim 22 wherein said first output line of said differential amplifier circuit is a non-inverting output terminal and wherein said second output line of said differential amplifier circuit is an inverting output terminal.

37. The balanced transimpedance amplifier circuit as recited in claim 22 wherein said first amplifier circuit includes:

a transistor having a control terminal coupled to said first capacitor and a second terminal connected to a first power supply terminal; and

a load resistor connected between a third terminal of said transistor and a second power supply terminal.

38. The balanced transimpedance amplifier circuit as recited in claim 37 wherein a voltage drop across said transistor summed with a voltage drop across said load resistor equals a difference in the voltage levels between said first and second power supply terminals.

39. The balanced transimpedance amplifier circuit as recited in claim 22 wherein said first voltage offset means is connected to the first output line of said differential amplifier circuit and to said first feedback network, and wherein said second voltage offset means is connected to the second output line of said differential amplifier circuit and to said second feedback network.

40. A method for biasing a balanced transimpedance amplifier circuit, said transimpedance amplifier circuit including a first and a second amplifier circuit for amplifying signals at a first and a second input line, respectively, a first feedback network coupled between a first output line of said transimpedance amplifier circuit and said first input line, and a second feedback network coupled between a second output line of said transimpedance amplifier circuit and said second input line, said method comprising the steps of:

DC level shifting a first signal at said first output line;

DC level shifting a second signal at said second output line;

providing said first DC level shifted signal to said first input line through said first feedback network;

providing said second DC level shifted signal to said second input line through said second feedback network;

AC coupling said first input line to an input node of said first amplifier circuit; and

AC coupling said second input line to an input node of said second amplifier circuit;

whereby a bias voltage across said first and second input lines is established independent of the voltage levels at the input nodes of said first and second amplifier circuits.

41. The method for biasing a balanced transimpedance amplifier circuit as recited in claim 40 further comprising the step of controlling the gain of said transimpedance amplifier circuit.

42. The method for biasing a balanced transimpedance amplifier circuit as recited in claim 40 further comprising the steps of:

providing an output signal of said first amplifier circuit to an input node of a differential amplifier circuit; and

providing an output signal from said second amplifier circuit to a second input node of said differential amplifier circuit.