Fully balanced transimpedance amplifier with low noise and wide bandwidth
First Claim
1. A balanced transimpedance amplifier circuit comprising:
- a first amplifier circuit for amplifying a first signal at a first input line;
a second amplifier circuit for amplifying a second signal at a second input line;
a first capacitor coupled between said first input line and an input node of said first amplifier circuit;
a second capacitor coupled between said second input line and an input node of said second amplifier circuit;
a first feedback network coupled between an output line of said first amplifier circuit and said first input line;
a second feedback network coupled between an output line of said second amplifier circuit and said second input line;
a first voltage offset means coupled in series with said first feedback network; and
a second voltage offset means coupled in series with said second feedback network.
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Accused Products
Abstract
A circuit is provided that solves the problem of implementing a fully balanced (differential) transimpedance amplifier with low-noise and wide bandwidth. This is accomplished by direct coupling the feedback resistors from the outputs of the amplifier to the inputs without the use of a blocking capacitor. The low frequency response is thereby improved and the problems created by a DC bias resistor that degrades the noise performance and, in some case, restricts the dynamic range (caused by pulse width distortion for large signals) are eliminated. The amplifier achieves higher voltage gain than prior designs and also results in lower noise and wider bandwidth. The differential nature of the amplifier provides good power supply rejection. While the preferred embodiment is particularly well-suited to GaAs MESFET technology, the invention can also be applied to silicon bipolar and MOS technology.
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Citations
42 Claims
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1. A balanced transimpedance amplifier circuit comprising:
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a first amplifier circuit for amplifying a first signal at a first input line; a second amplifier circuit for amplifying a second signal at a second input line; a first capacitor coupled between said first input line and an input node of said first amplifier circuit; a second capacitor coupled between said second input line and an input node of said second amplifier circuit; a first feedback network coupled between an output line of said first amplifier circuit and said first input line; a second feedback network coupled between an output line of said second amplifier circuit and said second input line; a first voltage offset means coupled in series with said first feedback network; and a second voltage offset means coupled in series with said second feedback network. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. A balanced transimpedance amplifier circuit comprising:
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a first amplifier stage including a first amplifier circuit for amplifying a first signal at a first input line and a second amplifier circuit for amplifying a second signal at a second input line; a second amplifier stage including a differential amplifier circuit having a first input node coupled to an output node of said first amplifier circuit and having a second input node coupled to an output node of said second amplifier circuit; a first capacitor coupled between said first input line and an input node of said first amplifier circuit; a second capacitor coupled between said second input line and an input node of said second amplifier circuit; a first feedback network coupled between a first output line of said differential amplifier circuit and said first input line; a second feedback network coupled between a second output line of said differential amplifier circuit and said second input line; a first voltage offset means coupled in series with said first feedback network; and a second voltage offset means coupled in series with said second feedback network. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39)
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40. A method for biasing a balanced transimpedance amplifier circuit, said transimpedance amplifier circuit including a first and a second amplifier circuit for amplifying signals at a first and a second input line, respectively, a first feedback network coupled between a first output line of said transimpedance amplifier circuit and said first input line, and a second feedback network coupled between a second output line of said transimpedance amplifier circuit and said second input line, said method comprising the steps of:
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DC level shifting a first signal at said first output line; DC level shifting a second signal at said second output line; providing said first DC level shifted signal to said first input line through said first feedback network; providing said second DC level shifted signal to said second input line through said second feedback network; AC coupling said first input line to an input node of said first amplifier circuit; and AC coupling said second input line to an input node of said second amplifier circuit; whereby a bias voltage across said first and second input lines is established independent of the voltage levels at the input nodes of said first and second amplifier circuits. - View Dependent Claims (41, 42)
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Specification