Transmission system for the synchronous digital hierarchy
First Claim
1. A transmitter for synchronous digital signals to be transmitted as a series of containers, comprisinga buffer into which newly arrived data for one of said containers are written, and from which stored data for said one container are read,a write address generator and a read address generator, for respectively providing write addresses and read addresses of locations in the buffer where said newly arrived data are to be written and said stored data are to be read, respectively,means for detecting the presence of positive and negative justification locations in said newly arrived data, and generating location presence signals responsive to detection of presence of such locations,an output circuit receiving said stored data read from said buffer, anda justification decision circuit comprising subtractor means for determining a difference between said write addresses and said read addresses;
- low-pass filter means receiving said location presence signals, and providing a low-pass filtered location presence value; and
means for combining said difference and said low-pass filtered location presence value, and forming a justification signal based thereon,responsive to said justification signal, said output circuit inserting justification locations in said stored data read from said buffer.
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Accused Products
Abstract
A digital transmission system having at least one adaptation circuit for compensating for phase variations of a STM-N signal. For inserting justification locations for at least one container of the STM-N signal, the adaptation circuit (8) includes a buffer (17, 51), a write address generator (16, 53), a read address generator (18, 61) a justification decision circuit (24, 60) and an output circuit (19, 62). The buffer stores container data in which justification locations may be inserted. The write address generator provides write addresses for data to be written in the buffer, and the read address generator provides read addresses in the buffer. In one embodiment differences between the read and write address values are combined with justification information which has been low pass filtered. In another embodiment these differences are low pass filtered and used for forming the justification decision signal. The output circuit inserts positive or negative justification locations in data read from the buffer to form the container.
37 Citations
25 Claims
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1. A transmitter for synchronous digital signals to be transmitted as a series of containers, comprising
a buffer into which newly arrived data for one of said containers are written, and from which stored data for said one container are read, a write address generator and a read address generator, for respectively providing write addresses and read addresses of locations in the buffer where said newly arrived data are to be written and said stored data are to be read, respectively, means for detecting the presence of positive and negative justification locations in said newly arrived data, and generating location presence signals responsive to detection of presence of such locations, an output circuit receiving said stored data read from said buffer, and a justification decision circuit comprising subtractor means for determining a difference between said write addresses and said read addresses; - low-pass filter means receiving said location presence signals, and providing a low-pass filtered location presence value; and
means for combining said difference and said low-pass filtered location presence value, and forming a justification signal based thereon,responsive to said justification signal, said output circuit inserting justification locations in said stored data read from said buffer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
- low-pass filter means receiving said location presence signals, and providing a low-pass filtered location presence value; and
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14. A transmitter for synchronous digital signals to be transmitted as a series of containers, comprising
a buffer into which newly arrived data for one of said containers are written, and from which stored data for said one container are read, a write address generator and a read address generator, for respectively providing write addresses and read addresses of locations in the buffer where said newly arrived data are to be written and said stored data are to be read, respectively, an output circuit receiving said stored data read from said buffer, and a justification decision circuit comprising subtractor means for determining a difference between said write addresses and said read addresses; - low-pass filter means receiving said difference, and providing a low-pass filtered difference value based directly on said difference between said write addresses and said read addresses, wherein a difference determined at a later instant has a greater effect on said low-pass difference value than a difference determined at an earlier instant and means for forming a justification signal based on said low-pass filtered difference value,
responsive to said justification signal, said output circuit inserting justification locations between said stored data read from said buffer.
- low-pass filter means receiving said difference, and providing a low-pass filtered difference value based directly on said difference between said write addresses and said read addresses, wherein a difference determined at a later instant has a greater effect on said low-pass difference value than a difference determined at an earlier instant and means for forming a justification signal based on said low-pass filtered difference value,
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15. A transmitter for synchronous digital signals to be transmitted as a series of containers, comprising
a buffer into which newly arrived data for one of said containers are written, and from which stored data for said one container are read, wherein said one container comprises at least one frame transmitted over a frame time interval, a write address generator and a read address generator, for respectively providing write addresses and read addresses of locations in the buffer where said newly arrived data are to be written and said stored data are to be read, respectively, an output circuit receiving said stored data read from said buffer, and a justification decision circuit comprising subtractor means for determining a difference between said write addresses and said read addresses, characterized in that said justification decision circuit further comprises low-pass filter means receiving said difference and comprising an accumulator having an accumulator output, an adder, and first and second multipliers, and providing a low-pass filtered difference value; - and means for forming a justification signal based on said low-pass filtered difference value, and wherein
said first multiplier receives and multiplies said difference by a first factor to form a first multiplied signal, said second multiplier multiplies said accumulator output by the negative of said first factor for providing a feedback signal to said adder at least once per four-frame time interval during the forming of a read address, and said adder receives and adds said feedback signal and said first and second multiplied signals, to form an adder output which is supplied to said accumulator, responsive to said justification signal said output circuit inserting justification locations between said stored data read from said buffer. - View Dependent Claims (16)
- and means for forming a justification signal based on said low-pass filtered difference value, and wherein
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17. A transmitter for synchronous digital signals to be transmitted as a series of containers, comprising
a buffer into which newly arrived data for one of said containers are written, and from which stored data for said one container are read, a write address generator and a read address generator, for respectively providing write addresses and read addresses of locations in the buffer where said newly arrived data are to be written and said stored data are to be read, respectively, an output circuit receiving said stored data read from said buffer, and a justification decision circuit comprising subtractor means for determining a difference between said write addresses and said read addresses, characterized in that said justification decision circuit further comprises low-pass filter means receiving said difference and providing a low-pass filtered difference value based directly on said difference between said write addresses and said read addresses; - and means for forming a justification signal based on said low-pass filtered difference value,
said means for forming comprises means for accumulating said low-pass filtered difference value and values of said difference over a given time for calculating a mean value, and means for comparing said mean value with a lower and an upper peak value;
responsive to said mean value being smaller than the lower peak value, said justification signal having a negative value for forming a negative justification location; and
responsive to said mean value being larger than the upper peak value, said justification signal having a positive value for forming a positive justification locationresponsive to said justification signal, said output circuit inserting justification locations between said stored data read from said buffer. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25)
- and means for forming a justification signal based on said low-pass filtered difference value,
Specification