Overpressure-protected, polysilicon, capacitive differential pressure sensor and method of making the same

• US 5,344,523 A
• Filed: 11/12/1993
• Issued: 09/06/1994
• Est. Priority Date: 05/12/1992
• Status: Expired due to Fees

• Current Assignee: Invensys Systems Incorporated (Invensys PLC)
• Original Assignee: The Foxboro Company (Schneider Electric SE)
• Inventors: Chau, Kevin H. L., Fung, Clifford D.
• Primary Examiner(s): POWELL, WILLIAM A
• Application Number:
  US08/150,837
• Time in Patent Office: 298 Days
• Field of Search: 156/628, 156/647, 156/657, 156/662, 156/633, 156/629, 437/901, 437/919, 437/921, 437/927, 29/621.1, 73/724, 73/726
• US Class Current: 438/53
• CPC Class Codes: G01L 9/0073 using a semiconductive diaphragm
• CPC Class Codes: Y10S 438/928 Front and rear surface processing
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate
• CPC Class Codes: Y10T 29/43 Electric condenser making

Abstract

A capacitive differential pressure sensing device with pressure overrange protection and a method of making the same are described. The device employs a doped polysilicon diaphragm overlying a cavity in a doped single crystal silicon wafer having a port extending into the cavity from the opposite side. The cavity floor serves as an overrange protector.

Claims

1. A method for manufacturing a capacitive differential pressure sensing device comprising the steps of,

forming a cavity in the top surface of a single crystal silicon wafer to a prescribed depth with a floor of generally predetermined area at said prescribed depth, said floor lying parallel to said upper surface,

filling said cavity with a sacrificial spacer material so that the upper surface of the filled cavity forms a smooth continuous surface with the upper surface of said wafer,

depositing on said wafer top surface a layer of polysilicon extending over the filled cavity,

selectively doping a portion of the polysilicon layer overlaying the filled cavity to form a conductive p+ region,

anisotropically etching in the bottom surface of said wafer, parallel to said top surface, an opening creating an open passage to the floor of said filled cavity, the opening in the floor of said cavity being located away from the center of said floor, and

removing said spacer material in said cavity through said passage.

2. A method in accordance with claim 1 wherein said spacer material is silicon dioxide.

3. A method in accordance with claim 1 wherein a thin layer of dielectric material is coated on said wafer top surface prior to depositing said layer of polysilicon.

4. A method in accordance with claim 1 wherein said selective doping of the polysilicon layer is done by ion beam implantation.

5. A method in accordance with claim 1 wherein said passage and said cavity are passivated with an oxide material after said sacrificial spacer material has been removed.

6. A method in accordance with claim 1 wherein a second area of said polysilicon layer, separate from said first area is doped to an electrically conductive state to provide for an electrical contact to said wafer.