SOI substrate fabrication

• US 5,344,524 A
• Filed: 06/30/1993
• Issued: 09/06/1994
• Est. Priority Date: 06/30/1993
• Status: Expired due to Term

• Current Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Original Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Inventors: Sharma, Kalluri R., Liu, Michael S.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): DANG, TRUNG Q
• Application Number:
  US08/085,422
• Time in Patent Office: 433 Days
• Field of Search: 156/630, 437/61, 437/62, 437/974, 148/DIG. 12
• US Class Current: 438/459
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/76256 using silicon etch back techniques, e.g. BESOI, ELTRAN
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76275 Vertical isolation by bonding techniques
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 21/76289 Lateral isolation by air gap
• CPC Class Codes: Y10S 148/012 Bonding, e.g. electrostatic for strain gauges
• CPC Class Codes: Y10S 438/97 Specified etch stop material

Abstract

A back-etch silicon-on-insulator SOI process that has a silicon handle wafer with an oxide layer bonded at room temperature to a silicon device wafer with an etch stop and silicon device layer. The surfaces that are bonded at room temperature are first conditioned to be hydrophilic. After bonding, the edges of the layers are sealed. The silicon device wafer, the etch-stop layer and the device layer are boron doped. Most of the silicon device wafer is ground away. Then, the remaining portion of the silicon device wafer and the etch stop layer are chemically etched away, thereby leaving a uniform layer of silicon device layer on the oxide layer of the silicon handle wafer. Because the bonding, grinding and selective etching are performed at room temperature, inter-diffusion of the boron between the various layers is prevented and thus permits the selective etching process to result in a nearly perfect silicon device layer in terms of an even-surfaced, defect-free and thin layer on the buried oxide layer of silicon handle wafer. The resulting SOI wafer is then annealed at a high temperature, prior to device processing.

Claims

1. A method for fabricating a silicon-on-insulator substrate, comprising:

forming an etch-stop layer on a silicon device wafer;

forming a device layer on the etch-stop layer;

forming a dielectric layer on a silicon handle wafer;

making exposed surfaces of the dielectric layer and the device layer hydrophilic;

bonding the device layer and the dielectric layer at the exposed surfaces to each other at room temperature;

removing the silicon device wafer; and

removing the etch-stop layer wherein said removing steps are performed at room temperature.

2. The method of claim 1 further comprising sealing edges from the silicon device wafer to the silicon handle wafer subsequent to the bonding and prior to the removing of the silicon device wafer and the edge-stop layer.

3. The method of claim 2 further comprising annealing the bonding of the device layer and the dielectric layer.

4. The method of claim 3 wherein:

the removing of the silicon device wafer is effected by grinding and etching; and

the removing the of the etch-stop layer is effected by etching.

5. The method of claim 4 wherein the forming of the dielectric layer is effected by thermally oxidizing a surface of the silicon handle wafer.

6. The method of claim 5 wherein:

the etch-stop layer is a heavily doped single crystal layer; and

the device layer is a lightly doped single silicon layer.

7. The method of claim 6 wherein:

the forming of the etch-stop layer is effected by epitaxial deposition; and

the forming of the device layer is effected by epitaxial deposition.

8. The method of claim 7 wherein:

the device layer has a thickness at a value set between 0.01 and 2.0 microns; and

the device layer, subsequent to the removing of the etch-stop layer, has a surface variation within plus and minus 75 Angstroms.

9. The method of claim 8 wherein:

the silicon device wafer is lightly doped (p^-) with boron;

the etch-stop layer is heavily doped (p⁺⁺) with boron and co-doped with germanium; and

the silicon device layer is lightly doped (p^-) with boron.

10. The method of claim 9 wherein:

the making exposed surfaces of the dielectric layer and the device layer hydrophilic, prior to bonding the surfaces to each other, is effected by cleaning the exposed surfaces with an RCA solution;

the removing of the silicon device wafer by etching is effected with an application of ethylene diamine and pyrocatechol; and

the removing of the etch-stop layer by etching is effected with an application of 1HF;

3 HNO₃ ;

8 HAc.

11. A method for fabricating a silicon-on-insulator substrate, comprising:

oxidizing a surface of a silicon handle wafer, resulting in an oxidized surface on the silicon handle wafer;

epitaxially depositing a highly boron doped (p⁺⁺) single crystal layer as an etch-stop layer on a surface of a silicon device wafer;

epitaxially depositing lightly boron doped (p^-) silicon layer as a device layer on the etch-stop layer;

conditioning a first surface of the silicon device layer and the oxidized surface of the silicon handle wafer to be hydrophilic;

bonding, at room temperature, the first surface of the silicon device layer and the oxidized surface of the silicon handle wafer to each other, resulting in bonded surfaces;

sealing the bonded surfaces at a bond perimeter with a sealant;

removing a significant portion of the silicon device wafer by grinding;

etching away the remaining portion of the silicon device wafer;

etching away the etch-stop layer, to expose a second surface of the silicon device layer wherein said removing and etching steps are performed at room temperature; and

annealing the bonding of the first surface of the silicon device layer and the oxidized surface of the silicon handle wafer.

12. The method of claim 11 wherein the resulting silicon device layer has a thickness at a value between 0.01 and 2.0 microns, with a surface variation of plus and minus 75 Angstroms.

13. The method of claim 12 further comprising:

thermally forming an oxide on the second surface of the silicon device layer; and

removing the oxide on the second surface of the silicon device layer to make the silicon device layer thinner.

14. The method of claim 13 wherein the conditioning of the first surface of the silicon device layer and the oxidized surface of the silicon handle wafer is effected by cleaning the first surface and the oxidized surface with an RCA solution.

15. The method of claim 14 wherein:

the remaining portion of the silicon device wafer, that is etched away, has a thickness between twenty and fifty microns; and

the etch-stop layer has a thickness of about two microns.

16. The method of claim 14 wherein the annealing of the bonding of the first surface of the silicon device layer and the oxidized surface of the silicon handle wafer is performed at approximately 1000 degrees Centigrade for improved bond strength between the bonded surfaces of the silicon device layer and the silicon handle wafer.

17. The method of claim 15 wherein:

the silicon device wafer has a boron concentration of approximately 10¹⁵ atoms/cm³ ;

the etch-stop layer has a boron concentration of approximately 10²⁰ atoms/cm³ ; and

the silicon device layer has a boron concentration less than 10¹⁵ atoms/cm³.

18. The method of claim 17 wherein the etch-stop layer is co-doped with about ten percent germanium, to compensate tensile stress caused by small boron atoms with compressive stress caused by larger germanium atoms.

19. The method of claim 18 wherein:

the remaining portion of the silicon device wafer, that is etched away, is etched with ethylene diamine and pyrocatechol (EDP); and

the etch-stop layer, that is etched, is etched away with 1HF;

3 HNO₃ ;

8 HAc etchant.