Phase locked loop with loop gain stabilization circuit

• US 5,345,193 A
• Filed: 07/28/1993
• Issued: 09/06/1994
• Est. Priority Date: 07/28/1993
• Status: Expired due to Term

• Current Assignee: Anritsu Co (Anritsu Corporation)
• Original Assignee: Wiltron Company
• Inventors: Bradley, Donald A.
• Primary Examiner(s): Grimm, Siegfried H.
• Application Number:
  US08/098,519
• Time in Patent Office: 405 Days
• Field of Search: 331/15, 331/16, 331/17, 331/18, 331/25
• US Class Current: 331/16
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/16 Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
• CPC Class Codes: H03L 7/20 using a harmonic phase-locked loop, i.e. a loop which can be locked to one of a number of harmonically related frequencies applied to it H03L7/22 takes precedence

Abstract

A phase locked loop includes a linear phase detector responsive to a first signal having a predetermined range of frequencies and a second signal for comparing the relative phase of the first signal and the second signal, and a loop gain stabilization circuit coupled between the source of the first signal and the linear phase detector for reducing the magnitude of variations in the loop gain of the phase locked loop over the predetermined range of frequencies of the first signal source. An embodiment of the linear phase detector comprises a harmonic sampler/presteer circuit. The construction and operation of the loop gain stabilization circuit depends on whether the phase locked loop is being used in a frequency multiplying or dividing circuit.

Claims

1. A phase locked loop comprising:

a source of a first signal having a predetermined range of frequencies;

a source of a second signal;

a linear phase detector responsive to said first signal and said second signal for comparing the relative phase of said first signal and said second signal; and

a loop gain stabilization circuit means coupled between said source of said first signal and said linear phase detector for reducing the magnitude of variations in the loop gain of said phase locked loop over said predetermined range of frequencies of said first signal source.

2. A phase locked loop according to claim 1 wherein said source of a first signal comprises a VCO, said loop gain stabilization circuit means is coupled to the output of said VCO, said source of a second signal comprises an oscillator having a predetermined frequency F_D and means for multiplying said predetermined frequency F_D by a selected multiplying factor R.

3. A phase locked loop according to claim 2 wherein said predetermined range of frequencies of said first signal comprises approximately 600 MHz to 1180 MHz, said predetermined frequency F_D comprises approximately 10 MHz and said means for multiplying said predetermined frequency F_D comprises means for selectively multiplying said predetermined frequency F_D by a multiplying factor of from 60 to 118.

4. A phase locked loop according to claim 2 wherein said loop gain stabilization circuit means comprises means for reducing the magnitude of the variations in the loop gain of said phase locked loop to a predetermined magnitude over said predetermined range of frequencies of said first signal.

5. A phase locked loop according to claim 4 wherein said predetermined magnitude is approximately ±

one (1) dB over said predetermined range of frequencies of said first signal.

6. A phase locked loop according to claim 4 wherein said means for reducing the magnitude of variations in the loop gain of said phase locked loop comprises a filter network, said filter network comprising means for providing a resistance, means for providing a capacitance and means for providing an inductance.

7. A phase locked loop according to claim 6 wherein said filter network comprises:

means for coupling one end of a first resistor to an input terminal and the opposite end of the first resistor to ground by means of a first capacitor and to one end of an inductor;

means for coupling the opposite end of the inductor to ground through a second and a third capacitor; and

means for coupling a node between said second and third capacitor to ground through a second resistor and to an output terminal.

8. A phase locked loop according to claim 7 wherein said first and second resistors comprise approximately 71 ohms and 51 ohms, respectively, said first, second and third capacitors comprise approximately 19 picofarads, 3 picofarads, and 5 picofarads, respectively, and said inductor comprises approximately 8.8 nanohenries.

9. A phase locked loop according to claim 1 wherein said source of a first signal having a said predetermined range of frequencies comprises a source of a first signal having a frequency F_rf within said predetermined range of frequencies, said source of a second signal comprises a source of a sampling signal having a frequency F_s for sampling said first signal, said linear phase detector comprises a harmonic sampler circuit means responsive to said first signal and said sampling signal for comparing the relative phase of said first signal and said sampling signal, and said loop gain stabilization circuit means comprises a loop gain stabilization circuit means coupled between said source of said first signal and said harmonic sampler for reducing the magnitude of variations in the loop gain of said phase locked loop over said predetermined range of frequencies of said first signal source.

10. A phase locked loop according to claim 9 wherein said source of said first signal having a frequency F_rf within a predetermined range of frequencies comprises a VCO and said harmonic sampler circuit means comprises means for operating said harmonic sampler at a selected harmonic number H within a predetermined range of harmonic numbers H.

11. A phase locked loop according to claim 10 wherein said predetermined range of frequencies of said first signal comprises approximately 600 MHz to 1180 MHz and said predetermined range of harmonic numbers H is 60 to 118.

12. A phase locked loop according to claim 9 wherein said source of said first signal comprises a VCO and further comprising means responsive to an output of said harmonic sampler for controlling the frequency F_rf of said VCO within said predetermined range of frequencies.

13. A phase locked loop according to claim 12 wherein said frequency controlling means comprises an operational amplifier.

14. A phase locked loop according to claim 1 wherein said source of said first signal comprises an oscillator having said predetermined range of frequencies F_idle, and said source of said second signal comprises a VCO having a predetermined range of frequencies F_D and means for multiplying said range of frequencies F_D by a selected multiplying factor R, said loop gain stabilization circuit means comprises means for attenuating said first signal at a predetermined rate over said predetermined range of frequencies of said first signal and further comprising means responsive to an output of said linear phase detector for controlling the frequency of said VCO.

15. A phase locked loop according to claim 14 wherein said attenuating means comprises means for attenuating said first signal at the rate of approximately 6 dB/octave over said predetermined range of frequencies of said input signal.

16. A phase locked loop according to claim 15 wherein said means for attenuating said first signal at the rate of approximately 6 dB/octave over said predetermined range of frequencies comprises a filter network comprising means for providing a resistance, means for providing a capacitance and means for providing and inductance.

17. A phase locked loop according to claim 16 wherein said means for providing said resistance, said capacitance and said inductance comprises:

means for providing a first, a second and a third resistance;

means for providing a first, a second and a third capacitance;

means for coupling one end of said first capacitance providing means in series with an input terminal;

means for coupling the opposite end of said first capacitance providing means to one end of said inductance providing means;

means for coupling the opposite end of said first capacitance providing means to ground by means of said first resistance providing means;

means for coupling the opposite end of said inductance providing means to ground by means of said second resistance providing means and said second capacitance providing means and to one end of said third capacitance providing means;

means for coupling said third capacitance providing means to ground by means of said third resistance providing means; and

means for coupling said third capacitance providing means to an output terminal.

18. A phase locked loop according to claim 17 wherein said means for providing a first, a second and a third resistance comprises means for providing a resistance of 180 ohms, 180 ohms and 51 ohms, respectively, said means for providing a first, a second and a third capacitance comprises means for providing a capacitance of 10 pf, 3.3 pf and 10 pf, respectively, and said means for providing said inductance comprises means for providing an inductance of 47 nanohenries.

19. A phase locked loop according to claim 14 wherein said predetermined range of frequencies of said source of said first signal comprises approximately 600 Hz to 1180 MHz, said predetermined frequency F_D comprises a frequency in the range of approximately 8.3 MHz to 50 MHz and said means for multiplying said predetermined frequency F_D comprises means for selectively multiplying said predetermined frequency F_D by a multiplying factor R of from 12 to 96.

20. A phase locked loop according to claim 14 wherein said frequency controlling means comprises an operational amplifier.

21. A phase locked loop according to claim 14 wherein said source of a first signal having said predetermined range of frequencies comprises a source of a first signal having a frequency F_rf within said predetermined range of frequencies, said source of a second signal comprises a source of a sampling signal having a frequency F_s for sampling said first signal, said linear phase detector and said multiplying means comprises a harmonic sampler circuit means responsive to said first signal and said sampling signal for comparing the relative phase of said input signal and said sampling signal, and said loop gain stabilization circuit means comprises a loop gain stabilization circuit means coupled between said source of said first signal and said harmonic sampler for reducing the magnitude of variations in the loop gain of said phase locked loop over said predetermined range of frequencies of said first signal source.

22. A phase locked loop according to claim 21 wherein said source of said sampling signal comprises said VCO, said harmonic sampler circuit means comprises means for operating said harmonic sampler at a selected harmonic number H within a predetermined range of harmonic numbers H, and further comprising means responsive to an output of said harmonic sampler for controlling the frequency of said VCO.

23. A phase locked loop according to claim 21 wherein said range of frequencies of said first signal comprises approximately 600 MHz to 1180 MHz, the range of the frequencies of said sampling signal is approximately 8.3 MHz to 50 MHz and said predetermined range of harmonic numbers H is approximately 12 to 96.

24. A phase locked loop according to claim 14 wherein said predetermined range of frequencies of said first signal comprises a first predetermined range of frequencies and said source of said second signal comprises:

a VCO for providing an output signal having a frequency F_coarse within a second predetermined range of frequencies;

a source of a first and a second reference frequency F_ref1 and F_ref2 ;

means for mixing said output signal having said frequency F_coarse with one of said first and second reference frequencies;

means for multiplying the output of said mixing means by a multiplying factor R for providing said second signal; and

means responsive to an output of said linear phase detector for controlling the frequency of said VCO for providing said output signal having said frequency F_coarse within said second predetermined range of frequencies.

25. A phase locked loop according to claim 24 wherein said first reference frequency F_ref1 is selected when said frequency F_coarse is within a first predetermined range of frequencies and said second reference frequency F_ref2 is selected when said frequency F_coarse is within a second predetermined range of frequencies.

26. A phase locked loop according to claim 25 wherein said linear phase detector and said multiplying means comprises a harmonic sampler, said harmonic sampler circuit means comprises means for operating said harmonic sampler at a selected harmonic number H within a predetermined range of harmonic numbers H, and further comprising means responsive to an output of said harmonic sampler for controlling the frequency of said VCO.

27. A method of stabilizing the gain in a phase locked loop comprising the steps of:

providing a first signal having a frequency within a predetermined range of frequencies;

providing a second signal;

comparing the relative phase of said first signal and said second signal in a linear phase comparator; and

filtering said first signal for reducing the magnitude of variations in the loop gain of said phase locked loop over said predetermined range of frequencies of said first signal.

28. A method according to claim 27 wherein said step of providing said first signal having a frequency F_rf within a predetermined range of frequencies comprises the step of providing said first signal having a frequency F_rf within a predetermined range of frequencies from a voltage controlled oscillator (VCO).

29. A method according to claim 28 wherein said predetermined range of frequencies comprises approximately 600 MHz to 1180 MHz.

30. A method according to claim 27 wherein said step of providing said first signal having a frequency F_rf within a predetermined range of frequencies comprises the step of providing said first signal having a frequency F_rf within a predetermined range of frequencies from a voltage controlled oscillator (VCO) and further comprising the step of using an output of said linear phase comparator for controlling the frequency F_rf of said VCO within said predetermined range of frequencies.

31. A method according to claim 30 wherein said step of controlling the frequency of said VCO comprises the step of controlling the frequency of said VCO using an operational amplifier.

32. A method according to claim 27 wherein said step of comparing comprises the step of comparing the relative phase of said first signal and said second signal in a harmonic sampler circuit means and said step of providing said second signal comprises the step of providing a sampling signal using a VCO and further comprising the step of using an output of said harmonic sampler for controlling the frequency of said VCO within said predetermined range of frequencies.

33. A method according to claim 27 wherein said predetermined range of frequencies comprises a first predetermined range of frequencies and said step of providing said second signal comprises the steps of:

providing an output signal having a frequency F_coarse within a second predetermined range of frequencies;

providing a first reference frequency F_ref1 and a second reference frequency F_ref2 ;

mixing said output signal having said frequency F_coarse with one of said first and second reference frequencies; and

using an output of said linear phase detector for controlling the frequency of said VCO for providing said output signal having said frequency F_coarse within said second predetermined range of frequencies.

34. A method according to claim 33 wherein said first reference frequency F_ref1 is selected when said frequency F_coarse is within a first predetermined range of frequencies and the second reference frequency F_ref2 is selected when said frequency F_coarse is within a second predetermined range of frequencies.

35. A method according to claim 30 wherein said phase comparing step comprises the step of comparing said phase using a harmonic sampler having a first input for receiving a first signal having a frequency F_rf and a second input for receiving a sampling signal having a sampling frequency F_s and an output for providing an output signal having an intermediate frequency F_if and said step of filtering said first signal comprises the step of reducing the magnitude of variations in the loop gain of said phase locked loop to approximately ±

one (1) dB over said predetermined range of frequencies.

36. A method according to claim 32 wherein said phase comparing step comprises the step of using a harmonic sampler having a first input for receiving a first signal having a frequency F_rf and a second input for receiving the sampling signal having a sampling frequency F_s and an output for providing an output signal having an intermediate frequency F_if and said step of filtering said first signal comprises the step of attenuating said first signal at the rate of approximately 6 dB/octave over said predetermined range of frequencies of said first signal.

37. A method according to claim 35 wherein said step of reducing the magnitude of variations in the loop gain of said phase locked loop comprises the step of providing a filter network having a resistance, a capacitance and an inductance.

38. A method according to claim 37 wherein said step of providing said resistance, said capacitance and said inductance comprises the steps of:

providing a first and a second resistance;

providing a first, a second and a third capacitance;

coupling one end of said first resistance in series with an input terminal;

coupling the opposite end of said first resistance to one end of said inductance;

coupling the opposite end of said first resistance to ground by means of said first capacitance;

coupling the opposite end of said inductance to said second capacitance;

coupling said second capacitance to ground by means of said third capacitance and said second resistance coupled in parallel; and

coupling said second capacitance to an output terminal.

39. A method according to claim 38 wherein said steps of providing a first and a second resistance comprises the steps of providing a resistance of 71 ohms and 51 ohms, respectively, said steps of providing a first, a second and a third capacitance comprises the steps of providing a capacitance of 19 picofarads (pf) 3 pf and 5 pf, respectively, and said step of providing said inductance comprises the step of providing an inductance of 8.8 nanohenries.

40. A method according to claim 36 wherein said step of attenuating said first signal comprises the step of providing a filter network having a resistance, a capacitance and an inductance.

41. A method according to claim 40 wherein said step of providing said resistance, said capacitance and said inductance comprises the steps of:

providing a first, a second and a third resistance;

providing a first, a second and a third capacitance;

coupling one end of said first capacitance in series with an input terminal;

coupling the opposite end of said first capacitance to one end of said inductance;

coupling the opposite end of said first capacitance to ground by means of said first resistance;

coupling the opposite end of said inductance to ground by means of said second resistance and said second capacitance and to one end of said third capacitance;

coupling said third capacitance to ground by means of said third resistance; and

coupling said third capacitance to an output terminal.

42. A method according to claim 41 wherein said steps of providing a first, a second and a third resistance comprises the steps of providing a resistance of 180 ohms, 180 ohms and 51 ohms, respectively, said steps of providing a first, a second and a third capacitance comprises the steps of providing a capacitance of 10 pf, 3.3 pf and 10 pf, respectively, and said step of providing said inductance comprises the step of providing an inductance of 47 nanohenries.