Digital .SIGMA.-.DELTA. modulator
First Claim
1. A digital Σ
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modulator comprising;
input means for sequentially receiving a digital signal of one channel from digital signals of n (n is an integer of not less than
2) channels in response to a clock signal, the digital signal having k (k is an integer of not less than
3) bits;
subtracting means, connected to said input means, for subtracting a feedback signal from the digital signal of one channel input from said input means;
integrating means, connected to said subtracting means, for integrating a signal output from said subtracting means;
quantizing means, connected to said integrating means, for quantizing a signal output from said integrating means into a quantized value j (j is an integer falling within a range of 1<
j<
2K) and generating an output signal;
delay means, connected to said quantizing means, for delaying the output signal from said quantizing means by n clocks and generating the feedback signal; and
output means, connected to said quantizing means, for assigning the signal output from said quantizing means to n channels in accordance with the given order of the signals input by said input means, and outputting the signal.
1 Assignment
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Accused Products
Abstract
A counter counts a clock signal. A multiplexer sequentially inputs digital input signals each having a plurality of bits in accordance with an output signal from the counter. A subtracter subtracts a quantized output signal delayed by an n-clock delay element from the input signal. An integrator integrates an output signal from the subtracter. The quantizer quantizes an output from the integrator. The n-clock delay element delays the output signal from the quantizer by n clocks and supplies the delayed signal to the subtracter. A demultiplexer sequentially outputs output signals from the quantizer in accordance with the output signal from the counter. This demultiplexer outputs signals in the input order of the multiplexer.
29 Citations
18 Claims
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1. A digital Σ
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modulator comprising;input means for sequentially receiving a digital signal of one channel from digital signals of n (n is an integer of not less than
2) channels in response to a clock signal, the digital signal having k (k is an integer of not less than
3) bits;subtracting means, connected to said input means, for subtracting a feedback signal from the digital signal of one channel input from said input means; integrating means, connected to said subtracting means, for integrating a signal output from said subtracting means; quantizing means, connected to said integrating means, for quantizing a signal output from said integrating means into a quantized value j (j is an integer falling within a range of 1<
j<
2K) and generating an output signal;delay means, connected to said quantizing means, for delaying the output signal from said quantizing means by n clocks and generating the feedback signal; and output means, connected to said quantizing means, for assigning the signal output from said quantizing means to n channels in accordance with the given order of the signals input by said input means, and outputting the signal. - View Dependent Claims (2, 3, 4)
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5. A digital Σ
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modulator comprising;input means for sequentially receiving a digital signal of one channel from digital signals of n (n is an integer of not less than
2) channels in response to a clock signal, the digital signal having k (k is an integer of not less than
3) bits;m subtracting means each for subtracting a feedback signal from the digital signal of one channel input from said input means; m integrating means, connected to said m subtracting means, for integrating signals output from said m subtracting means, respectively; quantizing means, connected to said mth integrating means, for quantizing a signal output from said integrating means into a quantized value j (j is an integer falling within a range of 1<
j<
2K) and generating an output signal;delay means, connected to said quantizing means, for delaying the output signal from said quantizing means by n clocks and generating the feedback signal; and output means, connected to said quantizing means, for assigning the signal output from said quantizing means to n channels in accordance with the given order of the signals input by said input means, and outputting the signal. - View Dependent Claims (6, 7, 8, 9)
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10. A digital Σ
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modulator comprising;input means for sequentially receiving digital signals of two channels in units of channels; first subtracting means, connected to said input means, for subtracting a feedback signal from the signal of one channel input by said input means; first delay means, connected to said first subtracting means, for delaying a signal output from said first subtracting means; adding means, connected to said first delay means, for adding the feedback signal to a signal output from said first delay means; quantizing means, connected to said adding means, for quantizing a signal output from said adding means; second subtracting means, connected to said adding means and said quantizing means, for subtracting a signal output from said quantizing means from a signal output from said adding means; second delay means, connected to said second subtracting means, for delaying a signal output from said second subtracting means and outputting the feedback signal; and output means, connected to said quantizing means, for, assigning the output from said quantizing means to 2 channels in accordance with an input order in said input means. - View Dependent Claims (11, 12, 13, 14)
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15. A digital Σ
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modulator comprising;input means for dividing an n-bit (n is an integer of not less than
2) digital signal into i (i is an integer of not less than 2;
i<
n) signals and sequentially inputting the divided digital signals from an LSB side;subtracting means, connected to said input means, for subtracting a feedback signal from the digital signal input by said input means; integrating means, connected to said subtracting means, for integrating a signal output from said subtracting means i times; quantizing means, connected to said integrating means, for quantizing a signal output from said integrating means and generating an output signal; delay means, connected to said quantizing means, for delaying the output signal from said quantizing means by i clocks and generating the feedback signal; and output means, connected to said quantizing means, for outputting the output signal output from said quantizing means. - View Dependent Claims (16, 17, 18)
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Specification