Improved sigma-delta type analog-to-digital converter and method

• US 5,345,236 A
• Filed: 12/21/1992
• Issued: 09/06/1994
• Est. Priority Date: 12/21/1992
• Status: Expired due to Term

• Current Assignee: Intersil Corporation (Renesas Electronics Corporation)
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Sramek, John Jr.
• Primary Examiner(s): Young, Brian K.
• Application Number:
  US07/993,585
• Time in Patent Office: 624 Days
• Field of Search: 341/141, 341/155, 341/143, 375/26, 375/27
• US Class Current: 341/144
• CPC Class Codes: H03M 3/474 using time-division multiplexing

Abstract

A multiplexed sigma delta analog-to-digital (A/D) converter for low frequency applications has a single oversampling modulator together with a relatively high cutoff lowpass filter together with individual line frequency (50 or 60 Hz) rejection filters for each output channel.

Claims

1. A multiplexed sigma delta analog-to-digital converter, comprising:

(a) a sigma delta modulator with a modulator input and a modulator output;

(b) an input multiplexer coupled between N signal inputs and said modulator input;

(c) a digital filter coupled to said modulator output, said digital filter having a passband frequency of at least N times Fb, where Fb is a bandwidth for signals at said N signal inputs;

(d) an output multiplexer coupled between said digital filter and N output filters; and

(e) wherein said input and output multiplexers correlate said N output filters to said N signal inputs, and each one of said N output filters filters out a line frequency, Fline, where the frequency Fline is greater than Fb but less than N times Fb.

2. The converter of claim 1, wherein:

(a) each one of said N output filters is an averaging filter; and

(b) said input multiplexer selects each one of said N signal inputs for K equispaced time intervals during each period of the frequency Fline;

with K being a positive integer greater than 1, and each one of said N output filters averages K outputs of said digital filter corresponding to one of said N signal inputs.

3. The converter of claim 2, wherein

said digital filter is a comb filter with -3 dB down point greater than about N times Fb.

4. The converter of claim 2, wherein:

(a) N Equals 8;

(b) K equals 4; and

(c) The line frequency Fline equals the frequency of an AC power line voltage which may be approximately 50 to 60 Hz.

5. The converter of claim 2, wherein:

(a) said modulator includes (i) one or more analog integrators in series and coupled to said modulator input, (ii) a digitizer coupled to said one or more integrators and connected to said modulator output, (iii) one or more digital-to-analog converters feeding back the output of said digitizer to said analog integrators;

(b) said digital filter includes one or more digital accumulators with each one of said digital accumulators corresponding to one of said integrators; and

(c) wherein said sigma-delta modulator and said digital filter includes reset means and wherein a reset of said modulator and said digital filter resets each of said one or more integrators and each one of said one or more accumulators.

6. The converter of claim 5, wherein

said digitizer is a comparator.

7. An analog-to-digital converter, said sampling converter

(a) a sampling analog-to-digital converter, said sampling converter sampling at a rate of F;

where F is an integer multiple of a frequency f_noise and outputting a digital data stream; and

(b) an averaging filter coupled to said sampling converter, said averaging filter averaging elements of said data stream corresponding to samplings of said sampling converter offset by a time equal to 1/(Nf_noise) seconds;

where N is a factor of said integer multiple.

8. The converter of claim 7, wherein

(a) said sampling analog-to-digital converter is a sigma delta converter;

(b) said f_noise is the frequency of an AC power line voltage; and

(c) N equals 4.

9. The converter of claim 8 wherein:

(a) said sigma delta converter includes a modulator and a digital filter;

(b) said modulator includes (i) one or more analog integrators in series and coupled to said modulator input, (ii) a digitizer coupled to said one or more integrators and connected to said modulator output, (iii) one or more digital-to-analog converters feeding back the output of said digitizer to said analog integrators;

(c) said digital filter includes one or more digital accumulators with each one of said accumulators corresponding to one of said integrators; and

(d) wherein said sigma delta modulator and said digital filter includes reset means and wherein a reset of said modulator and said digital filter resets each of said one or more accumulators.

10. A method of filtering the output of a sigma delta modulator, comprising the steps of:

(a) applying an output stream from a sigma delta modulator to a low pass digital filter having a cutoff frequency greater than a frequency Fline where Fline is the frequency of a periodic noise source; and

(b) averaging the outputs of said low pass digital filter at a rate which is N times the frequency, Fline, for integers of N greater than 1.