High speed serrodyne digital frequency translator

• US 5,345,239 A
• Filed: 06/16/1988
• Issued: 09/06/1994
• Est. Priority Date: 11/12/1985
• Status: Expired due to Fees

• Current Assignee: Systron Donner Corporation
• Original Assignee: Systron Donner Corporation
• Inventors: Wan, Lawrence, Madni, Asad M.
• Primary Examiner(s): Hellner, Mark
• Application Number:
  US07/219,825
• Time in Patent Office: 2,273 Days
• Field of Search: 342/13, 342/14, 342/175, 328/55, 328/155, 307/262, 307/511, 333/109, 333/139, 333/156
• US Class Current: 342/14
• CPC Class Codes: G01S 7/38 Jamming means, e.g. producing false echoes
• CPC Class Codes: H03D 2200/0078 using a switched phase shifter or delay line
• CPC Class Codes: H03D 7/00 Transference of modulation from one carrier to another, e.g. frequency-changing H03D9/00, H03D11/00 take precedence; dielectric amplifiers, magnetic amplifiers, parametric amplifiers used as a frequency-changers H03F
• CPC Class Codes: H03D 7/125 with field effect transistors
• CPC Class Codes: H03D 7/14 Balanced arrangements
• CPC Class Codes: H03D 9/0658 by means of semiconductor devices having more than two electrodes

Abstract

A high-speed serrodyne digital frequency translator utilizes a digital phase-shifter, for example, of series coupled Schiffman type cells, which have reference and delay paths which are switched by three-terminal devices of the gallium arsenide FET type. No bias voltages are used and the FETS are driven by the output of a binary divider network which in turn is composed of GaAs FETS as active elements. Thus switching in the picosecond range results.

Claims

1. Serrodyne phase-shifter apparatus for receiving radar or other microwave signals and phase shifting or frequency translating them comprising:

a solid-state variable phase shifter including a plurality of series coupled cells for inserting various and different phase-shifts into said received microwave signals by binary inputs to selected cells, each of said cells providing at least two expected phase shifts, one of which may be zero degrees, so that driving said binary inputs with an incrementally increasing binary number will cause step increases in expected phase shift of the series combination of the cells;

each of said cells including switching means responsive to a said binary input for causing such cell to have one of said two expected phase-shifts, swid switching means including a plurality of three terminal gallium arsenide field effect transistors (GaAs FET) having no d.c. bias and a gate input which is driven by said binary input and source and drain terminals, said switching means including a first pair of said FETs, having a common gate input for providing one of said two expected phase shifts by forming a conductive path for said signals between said source and drain terminals and a second pair of said FETs, having a common gate input for providing another of said two expected phase shifts by forming a conductive path for said signals between said source and drain terminals;

multi-bit counter means having a number of binary outputs corresponding to said binary inputs of said plurality of cells for providing said binary number;

and means for digitally driving said counter means.

2. Apparatus as in claim 1, where said counter means includes series connected flip-flop circuits, each with a pair of gallium arsenide FETS.

3. Apparatus as in claim 2 including clock means for driving said counter means.

4. Apparatus as in claim 1, where said cells are of the Schiffman type including reference path and a delay path and where said switching means alternately series connect such lines in response to said binary inputs.

5. Apparatus as in claim 1, where said cells are of the reflective type and said FETS have a source terminal grounded.

6. Apparatus as in claim 1, where said cells are of the loaded line type including inductive and capacitive legs and said FETS are connected as a pair to provide alternate switching between said legs.

7. Apparatus as in claim 1, where said cells are of the Hi-Low pass type having three pairs of inductive-capacitive legs and where six of said FETS provide switching between said pairs.

8. Apparatus as in claim 1, where said cells are d.c. coupled to each other.