Matrix array image sensor chip

• US 5,345,266 A
• Filed: 04/23/1992
• Issued: 09/06/1994
• Est. Priority Date: 09/23/1989
• Status: Expired due to Term

• Current Assignee: VLSI Vision Ltd.
• Original Assignee: VLSI Vision Ltd.
• Inventors: Denyer, Peter B.
• Primary Examiner(s): Razavi, Michael T.
• Assistant Examiner(s): Greening, Wendy R.
• Application Number:
  US07/842,107
• Time in Patent Office: 866 Days
• Field of Search: 358/213.23, 358/213.29, 358/212, 358/213.27, 358/213.11
• US Class Current: 348/300
• CPC Class Codes: H01L 27/14681 Bipolar transistor imagers
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: H04N 25/78 Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
• CPC Class Codes: H04N 3/1512 for MOS image-sensors, e.g. MOS-CCD H04N3/1581 takes precedence

Abstract

A matrix array image sensor integrated circuit chip is provided including horizontal and vertical scanning means with the sensor cells within columns of the array being associated with an analogue charge sense amplifier. The analogue charge sense amplifier includes a first amplifier in the form of an inverting charge integrator which provides a preliminary detection of the charge accumulated in the sensing cell by integrating the charge to produce a voltage which is capacitively stored in a voltage storage means. The sensing cell may then be reset by control logic while it is isolated from the stored voltage which is in turn selectively sampled using a switch to read out through a second amplifier stage to be provided as an output from the integrated circuit chip. A method for operation of the device in processing an image read cycle is also provided.

Claims

1. An integrated circuit for use as an image array sensor and providing an output signal to an off-circuit read device, said integrated circuit comprising,

a two-dimensional matrix array of sensing cells having a plurality of cell columns and a plurality of cell rows, each sensing cell having a photodiode and a transistor for reading from and writing to the photodiode,

horizontal scan means coupled to each cell in the array for scanning each cell row of the array of sensing cells,

vertical scan means coupled to each cell in the array for scanning each cell column of said array of sensing cells,

a plurality of analogue switch means each connected between at least one of said cell columns and the horizontal scan means for receiving image data from said cells, each of said analogue switch means being also connected by a common conductor to an output amplifier forming the output of the integrated circuit, each of said plurality of analogue switch means includes voltage storage means and first charge sensing amplifier means which provides a preliminary detection of charge created on each cell in response to radiation impinging thereon by converting the detected charge to a voltage using a first charge integrating circuit and capacitively storing the voltage in said voltage storage means, in the form of a charge corresponding to the cell charge, and that said output amplifier comprises a second charge sensing amplifier means which is selectively coupled to said voltage storage means of said analogue switch means, for providing an output signal to the off-circuit read device, said output signal being a voltage proportional to the charge in said voltage storage means.

2. An integrated circuit as claimed in claim 1 further characterized in that the sensing cell being "read" is reset using a signal from the vertical scan means and signals generated off-circuit of the array whilst said sensing cell is isolated from the signal stored in the voltage storage means.

3. An integrated circuit as claimed in claim 1 wherein the second charge sensing amplifier means is a second charge integrating circuit.

4. An integrated circuit as claimed in claim 1 wherein the first charge integrating circuit comprises an inverter consisting of two transistors arranged to provide negative gain and at least one capacitor located between input and output terminals of the inverter to provide charge integration via negative feedback to provide a voltage at the output of the invertor.

5. An integrated circuit as claimed in claim 1 wherein the first charge integrating circuit comprises an inverter consisting of, one transistor and one resistor, or an operational amplifier arranged to provide negative gain and at least one capacitor located between input and output terminals of the inverter to provide charge integration via negative feedback to provide a voltage at the output of the inverter.

6. An integrated circuit as claimed in claim 1 wherein the integrated circuit is fabricated using a technology selected from the group consisting of CMOS, PMOS, NMOS, Bipolar, BiMOS, BiCMOS and amorphous silicon technologies.

7. A camera having an electronic image capture means which includes a two-dimensional matrix array sensor, wherein said matrix array sensor comprises an integrated circuit according to claim 1.

10. An integrated circuit according to claim 1 wherein said integrated circuit is implemented using a technology selected from CMOS, PMOS, NMOS, Bipolar, BiMOS and BiCMOS technologies.

11. An integrated circuit according to claim 10 wherein said integrated circuit is implemented using a technology selected from CMOS and BiCMOS technologies.

12. An integrated circuit according to claim 10 wherein said two-dimensional matrix array of sensing cells has a small cell pitch of less than about 20 microns.

13. An integrated circuit according to claim 1 wherein each of said plurality of analogue switch means is connected to only one of said cell columns.

14. An integrated circuit according to claim 13 wherein each of said plurality of analogue switch means is located adjacent its associated cell column.

15. An integrated circuit according to claim 1 wherein said first charge sensing amplifier includes an inverter.

16. An integrated circuit according to claim 1 wherein said first charge integrating circuit comprises an inverter means for generating a voltage to balance said charge created on each cell.

17. An integrated circuit according to claim 1 wherein said first charge integrating circuit includes two transistors.

18. An integrated circuit according to claim 1 further including a plurality of switches, each of said switches connecting at least on of said voltage storage means to said output amplifier.

8. A method of detecting radiation incident upon an image sensor fabricated using integrated circuit technology in which the integrated circuit comprises a two dimensional matrix array of image sensing cells having a plurality of cell columns and a plurality of cell rows, each image sensing cell having a photodiode and a transistor for reading to and writing from the photodiode, horizontal scan means coupled to each cell in the array for scanning each cell row in the array, vertical scan means coupled to each cell in the array for scanning each cell column in the array, and a plurality of analogue switch means each connected between at least one of the cell columns and said horizontal scan means for receiving image data from each of said cells, each of said plurality of analogue switch means includes voltage storage means and first charge sensing amplifier means, each of said analogue switch means being also connected by a conductor to a output amplifier having its output connected to an external read-device for reading image signals from said output amplifier, said method being characterized by the steps of:

reading a cell from an associated one of said cell columns using a selected one of the plurality of analogue switch means by generating a voltage to balance charge in the cell created in response to incident radiation,

storing the voltage capacitively in the selected one of the plurality of analogue switch means in the form in the form of a charge corresponding to the cell charge, and

reading out the capacitively stored information in the selected one of the plurality of analogue switch means to the output amplifier.

9. A method as claimed in claim 8 further including the steps following said storing step of isolating the cell from the capacitively stored voltage using a switch which is actuated in response to off-circuit signals;

followed by,

reseting the cell by a combination of signals from the horizontal scan means and off-circuit signals.

19. An integrated circuit image array sensor comprising:

a two-dimensional matrix array of sensing cells having a plurality of cell columns and a plurality of cell rows, each of said sensing cells in said two-dimensional matrix array having a photodiode and a transistor for reading from and writing to the photodiode, each of said sensing cells in said two-dimensional matrix array generating a charge in response to radiation impinging on said cell to provide image data;

horizontal scan means coupled to each cell in said two-dimensional matrix array for scanning each cell row of the array of sensing cells;

vertical scan means coupled to each cell in said two-dimensional matrix array for scanning each cell column of said array of sensing cells;

a plurality of analogue switch means each connected between at least one of said cell columns and said horizontal scan means for receiving said image data from said cells,

each of said analogue switch means including charge sensing amplifier means for converting said charge to a voltage by integrating said charge and further including a voltage storage means for capacitively storing said voltage; and

an output amplifier which is selectively connected to each of said voltage storage means.

20. An integrated circuit for use as an image array sensor and providing an output signal to an off-circuit read device, said integrated circuit comprising,

a two-dimensional matrix array of sensing cells having a plurality of cell columns and a plurality of cell rows, each sensing cell having a photodiode and a transistor for reading from and writing to the photodiode,

horizontal scan means coupled to each cell in the array for scanning each cell row of the array of sensing cells,

vertical scan means coupled to each cell in the array for scanning each cell column of said array of sensing cells,

a plurality of analogue switch means each connected between at least one of said cell columns and the horizontal scan means for receiving image data from said cells, each of said analogue switch means being also connected by a common conductor to a output amplifier forming the output of the integrated circuit, each of said plurality of analogue switch means includes voltage storage means and first charge sensing amplifier means which provides a preliminary detection of charge created on each cell in response to radiation impinging thereon by converting the detected charge to a voltage using a first charge integrating circuit, said first charge integrating circuit comprising an inverter means for generating a voltage to balance said charge created on each cell, and capacitively storing the voltage in said voltage storage means, in the form of a charge corresponding to the cell charge, and that said output amplifier comprises a second charge sensing amplifier means which is selectively coupled to said voltage storage means of said analogue switch means, for providing an output signal to the off-circuit read device, said output signal being a voltage proportional to the charge in said voltage storage means.