Delay matching for video data during expansion and compression

• US 5,345,272 A
• Filed: 11/03/1992
• Issued: 09/06/1994
• Est. Priority Date: 06/01/1990
• Status: Expired due to Term

• Current Assignee: Thomson Consumer Electronics Incorporated (Vantiva SA)
• Original Assignee: Thomson Consumer Electronics Incorporated (Vantiva SA)
• Inventors: Doty, James H. II, Kranawetter, Greg A., Saeger, Timothy W., Ersoz, Nathaniel H.
• Primary Examiner(s): Groody, James J.
• Assistant Examiner(s): Burgess, Glenton B.
• Application Number:
  US07/940,878
• Time in Patent Office: 672 Days
• Field of Search: 358/12, 358/141, 358/16, 358/183, 358/22, 358/160
• US Class Current: 348/561
• CPC Class Codes: H04N 3/223 Controlling dimensions by maintaining the cathode-ray tube high voltage constant H04N3/185
• CPC Class Codes: H04N 3/27 Circuits special to multi-standard receivers
• CPC Class Codes: H04N 5/45 Picture in picture , e.g. displaying simultaneously another television channel in a region of the screen
• CPC Class Codes: H04N 7/007 Systems with supplementary picture signal insertion during a portion of the active part of a television signal, e.g. during top and bottom lines in a HDTV letter-box system
• CPC Class Codes: H04N 7/01 Conversion of standards , e.g. involving analogue television standards or digital television standards processed at pixel level
• CPC Class Codes: H04N 7/0105 using a storage device with different write and read speed
• CPC Class Codes: H04N 7/0122 the input and the output signals having different aspect ratios
• CPC Class Codes: H04N 9/641 Multi-purpose receivers, e.g. for auxiliary information H04N9/642 takes precedence

Abstract

Video luminance data from a video signal is selectably compressed and expanded in a first signal path including a first line memory. A second line memory in a parallel signal path processes video chrominance data from the video signal. A control circuit generates respective timing signals for writing data into each of the first and second memories and for reading data from each of first and second the line memories. A timing delay circuit for the control circuit, has video compression and expansion modes of operation. During the compression mode, reading of the second line memory is delayed relative to writing of the second line memory. During the expansion mode, writing of the first line memory is delayed relative to writing of the second line memory or reading of the second line memory is delayed relative to writing of the second line memory. The duration of the timing delays can be selected from a range of values. The line memories are first in first out (FIFO) devices having independently enabled write and read ports.

Claims

1. A video processing system, comprising:

means for compressing and expanding video luminance data, including a first line memory;

a second line memory for processing video chrominance data;

control means for generating respective timing signals for writing data into said first line memory and said second line memory and for reading data from said first line memory and said second line memory; and

,

a timing delay circuit for said control means, having video compression and expansion modes of operation, wherein during said compression mode reading of said second line memory is delayed relative to reading of said first line memory and during said expansion mode writing of said first line memory is delayed relative to writing of said second line memory.

2. The system of claim 1, further comprising means for controlling the duration of said timing delays over a range of selectable values.

3. The system of claim 1, wherein said first line memory and said second line memory are first in first out (FIFO) devices having independently enabled write and read ports.

4. The system of claim 1, wherein said means for compressing and expanding video luminance data further comprises interpolating means.

5. A video processing system, comprising:

means for compressing and expanding video luminance data, including a first line memory and interpolating means, said interpolating means imparting a propagation delay;

a second line memory for processing video chrominance data, said luminance and chrominance data having a delay mismatch as input or output signals of said circuit;

control means for generating respective timing signals for writing data into said first line memory and said second line memory and for reading data from said first line memory and said second line memory; and

,

a timing delay circuit for said control means, wherein during both video compression and expansion modes of operation reading of said second line memory is delayed relative to reading of said first line memory if said delay mismatch is less than said propagation delay imparted by said interpolating means.

6. The system of claim 5, further comprising means for controlling the duration of said timing delays over a range of selectable values.

7. The system of claim 5, wherein said first line memory and said second line memory are first in first out devices having independently enabled write and read ports.

8. A video processing system, comprising:

means for compressing and expanding video luminance data, including a first line memory;

a second line memory for processing video chrominance data;

control means for generating respective timing signals for writing data into said first line memory and said second line memory and for reading data from said first line memory and said second line memory; and

,

a timing delay circuit for said control means, having a mode of operation for video compression and at least one of two modes of operation for video expansion, wherein;

during said compression mode reading of said second line memory is delayed relative to reading of said first line memory;

during one of said expansion modes writing of said first line memory is delayed relative to writing of said second line memory, when said means for compressing and expanding video luminance data also includes interpolating means imparting a propagation delay less than a delay mismatch of said luminance and chrominance data as input or output signals of said system; and

,

during the other of said expansion modes reading of said second line memory is delayed relative to writing of said second line memory, when said means for compressing and expanding video luminance data also includes interpolating means imparting a propagation delay greater than a delay mismatch of said luminance and chrominance data as input or output signals of said system.

9. The system of claim 8, further comprising means for controlling the duration of said timing delay over a range of selectable values.

10. The system of claim 8, wherein said first and second line memories are first in first out (FIFO) devices having independently enabled write and read ports.