Method for generating power slits

• US 5,345,394 A
• Filed: 02/10/1992
• Issued: 09/06/1994
• Est. Priority Date: 02/10/1992
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: S-MOS Systems, Inc.
• Inventors: Hoang, Hy, Chuang, Tatao, Long, Tran, Lin, Chong M.
• Primary Examiner(s): Black, Thomas G.
• Assistant Examiner(s): MCFADDEN, SUSAN IRIS
• Application Number:
  US07/833,419
• Time in Patent Office: 939 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 395/750
• US Class Current: 716/54
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An automatic method of generating slits in power buses on a chip. The present invention includes three embodiments. The first embodiment is directed to a generic method of generating power slits. Once bus dimensions are identified, predetermined parameters for optimal power slit size and number are used to automatically generate a power slit layer for the mask database. The second embodiment is a continuation of the first embodiment and is directed to a method of generating power slits for an orthogonal corner case; where two buses overlap at 90° angles. This is performed by locating all corner cases. Power slits are removed within a cross (corner/intersect) area of overlapping buses. At this point power slits from overlapping buses are extended across the corner/intersect area. The extension lines are logically ANDed together resulting in points within the corner/intersect area where the extension lines intersect. These intersection points indicate where new types of power slits, called "holes", can be generated. The third embodiment is directed to a method of generating power slits for non-orthogonal corner case. It is generally identical to the second embodiment.

Claims

1. A method for generating slits in a power bus located on a chip, comprising the steps of:

(1) locating a bus;

(2) determining a width for said bus;

(3) determining a length for said bus;

(4) dividing said width by a maximum width of the power slits plus a first spacing distance between the power slits, resulting in a first number indicating how many power slit(s) to generate in a width direction of said bus;

(5) dividing said length by a minimum length of the power slits plus a second spacing distance between the power slits, resulting in a second value indicating how many power slit(s) to generate in a length direction of said bus; and

(6) generating a plurality of power slits according to steps (4) and (5) on said bus utilizing said first and second spacing distance between the power slits in said width and said length directions of said bus, respectively.

2. A method according to claim 1, wherein said steps (2) and (3) further comprise the steps of:

(a) assigning a starting-point and an endpoint corresponding to boundaries of said bus in a horizontal direction;

(b) subtracting said starting-point from said endpoint resulting in a first absolute value;

(c) assigning a starting-point and an endpoint corresponding to boundaries of said bus in a vertical direction;

(d) subtracting said starting-point from said endpoint resulting in a second absolute value;

(e) comparing said first value with said second value to determine which is greater;

(f) assigning said greater value as said length of said bus; and

(g) assigning which ever value is smaller according to step (e) as said width of said bus.

3. A method according to claim 2, wherein said starting-points and said endpoints are coordinate locations obtained from a mask layout data base.

4. A method according to claim 1, wherein said step (2) further comprises the steps of comparing said width to a minimum standard value and returning to step (1) if said minimum standard value is greater than said width for said bus.

5. A method for generating slits in a power bus located on a chip, comprising the steps of:

(1) locating a bus;

(2) determining a width for said bus;

(3) determining a length for said bus;

(4) dividing said width by a maximum width of the power slits plus a first spacing distance between the power slits, resulting in a first number indicating how many slit(s) to generate in a width direction of said bus;

(5) dividing said length by a minimum length of the power slits plus a second spacing distance between the power slits, resulting in a second value indicating how many slit(s) to generate in a length direction of said bus;

(6) generating a plurality of power slits according to steps (4) and (5) on the said bus utilizing said first and second spacing distance between the power slits in said width and said length directions of said bus, respectively;

(7) repeating steps (1) through (6) until all buses in a defined area have power slits;

(8) identifying if any buses in said defined area overlap to form an orthogonal cross section;

(9) removing all power slits in said orthogonal cross section;

(10) extending first pointer line(s) from a first power slit(s) of a first bus to an opposite boundary side of said cross area to connect said first power slit(s) of said first bus;

(11) extending second pointer line(s) from a power slit(s) of a second bus to an opposite boundary side of said cross area from said second power slits of said second bus;

(12) intersecting, logically, said first pointer line(s) with said second pointer line(s) forming a defined hole indicating where to generate power slits; and

(13) generating power slit(s) where said defined holes are located.

6. A method according to claim 5 wherein said step (12) includes logically ANDing, said first pointer line(s) with said second pointer line(s) to form defined holes indicating where to generate power slits.

7. A method according to claim 5, wherein said step (8) further comprises the steps of evaluating logically where two buses share coordinate values that intersect.

8. A method according to claim 7, wherein said evaluating step includes searching for two buses that have overlapping coordinate values.

9. A method according to claim 5, wherein said extending step in said step (10) includes extending pointer lines in a 90°

direction.

10. A method according to claim 5, wherein said extending step in said step (10) includes extending pointer lines in a 180°

direction.

11. A method according to claim 5, wherein said extending step in said step (11) includes extending pointer lines in a 90°

direction.

12. A method according to claim 5, wherein said extending step in said step (11) includes extending pointer lines in a 180°

direction.

13. An apparatus having a plurality of buses, comprising:

a first bus that intersects a second bus within the same conductive layer to form a cross area, said first bus having first power slits and first pointer lines extending from said first power slits through said cross area and said second bus having second power slits and second pointer lines extending from said second power slits through said cross area, wherein said cross area is void of power slits, said cross area comprising holes located at intersection points where the first pointer lines and the second pointer lines intersect.