Method for generating power slits
First Claim
1. A method for generating slits in a power bus located on a chip, comprising the steps of:
- (1) locating a bus;
(2) determining a width for said bus;
(3) determining a length for said bus;
(4) dividing said width by a maximum width of the power slits plus a first spacing distance between the power slits, resulting in a first number indicating how many power slit(s) to generate in a width direction of said bus;
(5) dividing said length by a minimum length of the power slits plus a second spacing distance between the power slits, resulting in a second value indicating how many power slit(s) to generate in a length direction of said bus; and
(6) generating a plurality of power slits according to steps (4) and (5) on said bus utilizing said first and second spacing distance between the power slits in said width and said length directions of said bus, respectively.
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Accused Products
Abstract
An automatic method of generating slits in power buses on a chip. The present invention includes three embodiments. The first embodiment is directed to a generic method of generating power slits. Once bus dimensions are identified, predetermined parameters for optimal power slit size and number are used to automatically generate a power slit layer for the mask database. The second embodiment is a continuation of the first embodiment and is directed to a method of generating power slits for an orthogonal corner case; where two buses overlap at 90° angles. This is performed by locating all corner cases. Power slits are removed within a cross (corner/intersect) area of overlapping buses. At this point power slits from overlapping buses are extended across the corner/intersect area. The extension lines are logically ANDed together resulting in points within the corner/intersect area where the extension lines intersect. These intersection points indicate where new types of power slits, called "holes", can be generated. The third embodiment is directed to a method of generating power slits for non-orthogonal corner case. It is generally identical to the second embodiment.
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Citations
13 Claims
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1. A method for generating slits in a power bus located on a chip, comprising the steps of:
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(1) locating a bus; (2) determining a width for said bus; (3) determining a length for said bus; (4) dividing said width by a maximum width of the power slits plus a first spacing distance between the power slits, resulting in a first number indicating how many power slit(s) to generate in a width direction of said bus; (5) dividing said length by a minimum length of the power slits plus a second spacing distance between the power slits, resulting in a second value indicating how many power slit(s) to generate in a length direction of said bus; and (6) generating a plurality of power slits according to steps (4) and (5) on said bus utilizing said first and second spacing distance between the power slits in said width and said length directions of said bus, respectively. - View Dependent Claims (2, 3, 4)
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5. A method for generating slits in a power bus located on a chip, comprising the steps of:
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(1) locating a bus; (2) determining a width for said bus; (3) determining a length for said bus; (4) dividing said width by a maximum width of the power slits plus a first spacing distance between the power slits, resulting in a first number indicating how many slit(s) to generate in a width direction of said bus; (5) dividing said length by a minimum length of the power slits plus a second spacing distance between the power slits, resulting in a second value indicating how many slit(s) to generate in a length direction of said bus; (6) generating a plurality of power slits according to steps (4) and (5) on the said bus utilizing said first and second spacing distance between the power slits in said width and said length directions of said bus, respectively; (7) repeating steps (1) through (6) until all buses in a defined area have power slits; (8) identifying if any buses in said defined area overlap to form an orthogonal cross section; (9) removing all power slits in said orthogonal cross section; (10) extending first pointer line(s) from a first power slit(s) of a first bus to an opposite boundary side of said cross area to connect said first power slit(s) of said first bus; (11) extending second pointer line(s) from a power slit(s) of a second bus to an opposite boundary side of said cross area from said second power slits of said second bus; (12) intersecting, logically, said first pointer line(s) with said second pointer line(s) forming a defined hole indicating where to generate power slits; and (13) generating power slit(s) where said defined holes are located. - View Dependent Claims (6, 7, 8, 9, 10, 11, 12)
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13. An apparatus having a plurality of buses, comprising:
- a first bus that intersects a second bus within the same conductive layer to form a cross area, said first bus having first power slits and first pointer lines extending from said first power slits through said cross area and said second bus having second power slits and second pointer lines extending from said second power slits through said cross area, wherein said cross area is void of power slits, said cross area comprising holes located at intersection points where the first pointer lines and the second pointer lines intersect.
Specification