Programmable digital signal processor system for processing electrical power signals

• US 5,345,409 A
• Filed: 03/25/1993
• Issued: 09/06/1994
• Est. Priority Date: 03/25/1993
• Status: Expired due to Term

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Jacob, Philippe, McGrath, Donald T., Garverick, Steven L., Krisciunas, Joseph E.
• Primary Examiner(s): NGUYEN, LONG
• Application Number:
  US08/036,743
• Time in Patent Office: 530 Days
• Field of Search: 364/736, 364/724.10, 364/481, 364/483, 364/726, 341/77, 341/110
• US Class Current: 702/60
• CPC Class Codes: G01R 21/133 by using digital technique
• CPC Class Codes: G01R 22/10 using digital techniques

Abstract

A system for processing digital electrical power signals derived from at least one externally supplied, substantially continuous, substantially alternating, electrical signal having a primary or fundamental frequency, comprises: a multiply-accumulate arithmetic processor having three input ports with at least one input port for receiving the digital electrical power signals, an output port and a processor control port; a first memory unit for storing a plurality of processor control signals; a second and third memory unit each for storing a separate plurality of processor input signals; and a memory control unit having the capability to respectively couple the first memory unit to the processor control port, and the first processor input port to one of the second and third memory units for each cycle of the primary frequency so that newly received digital electrical power signals may be continually processed by the processor for a predetermined number of cycles.

Claims

1. A system for processing at least one externally derived electrical power signal, said signal being substantially continuous, substantially alternating, and having a primary frequency, said system comprising:

a multiply-accumulate processor having three input ports, an output port, and a processor control signal port, said multiply-accumulate processor performing, in response to predetermined processor control signals, predetermined arithmetic operations on digital input signals substantially derived from said at least one substantially continuous electrical signal and arriving at a substantially predetermined rate;

a first memory unit for storing a plurality of processor control signals;

a second and third memory unit, each for storing a separate plurality of processor digital input signals; and

a memory control unit which, in response to externally derived memory unit control signals, respectively couples said first memory unit to said processor control signal port, and the first processor input port to one of said second and third memory units for each successive cycle of the primary frequency so that the digital input signals derived from the substantially continuous electrical signal and provided to one of the three processor input ports are continually processed by said processor for a predetermined number of successive cycles of the primary frequency.

2. The system of claim 1, wherein the primary frequency is substantially 60 cycles per second.

3. The system of claim 1, wherein said memory control unit further couples said first processor input port from said second memory unit to said third memory unit substantially between two successive cycles of the primary frequency.

4. The system of claim 1, wherein said memory control unit further couples said first processor input port from said third memory unit to said second memory unit substantially between two successive cycles of the primary frequency.

5. The system of claim 1, and further comprising a fourth memory unit for storing a plurality of processor output signals;

and

wherein said processor includes a processor control signal decoder having a processor interface port coupled to said memory control unit for providing processor derived memory unit control signals;

said processor output port being coupled to said fourth memory unit, and said memory control unit storing processor output signals in said fourth memory unit in response to the processor derived memory unit control signals.

6. The system of claim 5, and further comprising:

at least one analog-to-digital converter providing quantized digital electrical signals on an output port thereof, substantially at the predetermined rate, said converter being responsive to the electrical signal substantially having a primary frequency;

said memory control unit coupling said converter output port to the second processor input port in response to the externally derived memory control unit signals.

7. The system of claim 6, wherein said converter comprises a sigma-delta modulator and a decimation filter coupled to the output of said sigma-delta modulator.

8. The system of claim 7, wherein said converter further comprises a parallel to serial binary interface coupled to the output port of said decimation filter.

9. The system of claim 8, wherein said parallel to serial binary interface comprises a shift register, and a latch coupled to the output port of the shift register.

10. The system of claim 6, and further comprising a plurality of other analog-to-digital converters, each of said converters comprising a sigma-delta modulator and a decimation filter coupled to the output port of the modulator, a cyclical register provides binary electrical signals on an output port at the predetermined rate, each of said decimation filters being coupled to an input port of said cyclical register, each of said modulators being responsive to an externally derived, substantially continuous substantially alternating, electrical signal substantially having the primary frequency of said one externally derived electrical power signal.

11. The system of claim 5, wherein said processor output port is also coupled to said first memory unit,

said memory control unit also storing processor output signals in said first memory unit in response to predetermined processor derived memory unit control signals.

12. The system of claim 11, and further comprising an external microprocessor, and a microprocessor interface coupling said memory control unit to said external microprocessor, said microprocessor interface for providing microprocessor derived memory unit control signals from said microprocessor to said memory control unit, the microprocessor derived memory unit control signals constituting the externally derived memory unit control signals, said microprocessor interface further for transferring electrical signals between said microprocessor and said memory control unit.

13. The system of claim 12, wherein said memory control unit has the capability to transfer stored electrical signals between said one of said memory units and said microprocessor interface in response to microprocessor derived memory unit control signals.

14. The system of claim 13, wherein said one of said memory units comprises said fourth memory unit.

15. The system of claim 14, wherein said memory control unit provides control to said first and fourth memory units so that processor output signals are stored in one of said first memory unit and said fourth memory unit for predetermined portions of a cycle of said primary frequency in response to processor derived memory unit control signals.

16. The system of claim 15, wherein at least one of said decimation filters comprises a programmable length decimation filter.

17. The system of claim 12, wherein said memory control unit, in response to microprocessor derived memory unit control signals, couples one of said second and third memory units to said microprocessor interface for each cycle of said primary frequency so as to transfer stored electrical signals between the memory unit thus coupled and said microprocessor,

said microprocessor generating during at least one cycle of said primary frequency a set of electrical signals for storage in one of said second and third memory units such that one of the signals of said set will control the number of converter output signals received by said processor in a later primary frequency cycle.

18. The system of claim 17, wherein said memory control unit further couples said interface from said second memory unit to said third memory unit in an interval substantially between two successive cycles of the primary frequency.

19. The system of claim 17, wherein said memory control unit further couples said interface from said third memory unit to said second memory unit in an interval substantially between two successive cycles of the primary frequency.

20. The system of claim 17, wherein said memory control unit has the capability to exchange said second and third memory units between said microprocessor interface and said second processor input port at the beginning of each cycle of the primary frequency so that the said interface and said second input port are respectively coupled to different memory units.

21. The system of claim 17, wherein said first memory unit incorporates processor control signals capable of executing a discrete fourier transform.

22. The system of claim 21, wherein said discrete fourier transform constitutes a recursive discrete fourier transform.

23. The system of claim 22, wherein said microprocessor incorporates a program for sampling predetermined selected frequencies for each of the externally derived alternating electrical signals on each cycle of the primary frequency.

24. The system of claim 23, wherein said microprocessor program has the capability to modify the selected frequencies sampled in response to the processor output signals transferred to said microprocessor from said fourth memory device.

25. The system of claim of claim 17, wherein said microprocessor incorporates a program having the capability to generate a set of processor input signals on each cycle of said primary frequency in response to the processor output signals generated on a previous cycle.

26. The system of claim 12, wherein each of said memory units comprises a respective random access memory.

27. The system of claim 11, wherein said memory control unit has the capability to switch said processor output signals between said first memory unit and said fourth memory unit and said second input port between said register output port and said first memory unit during each cycle of the primary frequency, whereby said system has the capability to further process said processor output signals