Clock generation

• US 5,345,449 A
• Filed: 02/25/1993
• Issued: 09/06/1994
• Est. Priority Date: 07/07/1989
• Status: Expired due to Term

• Current Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Original Assignee: Inmos Limited (STMicroelectronics NV)
• Inventors: Buckingham, Keith, Simpson, Robert J.
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): MARCELO, MELVIN C
• Application Number:
  US08/023,201
• Time in Patent Office: 558 Days
• Field of Search: 370/84, 370/112, 370/100.1, 307/269
• US Class Current: 370/518
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: H03K 5/00006 Changing the frequency modulating pulses H03K7/00; frequency dividers H03K21/00 - H03K29/00; additive or subtractive mixing of two pulse rates into one G06F7/605; pulse rate dividers G06F7/68
• CPC Class Codes: H03K 5/13 Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
• CPC Class Codes: H03K 5/151 with two complementary outputs

Abstract

In an integrated circuit, a multiplexor receives incoming data at a first rate and is controllable by a high rate clock signal to output that data serially at a second, higher rate. A processing device receives the data from the multiplexor at the higher rate and is controllable by a high rate clock signal to process that data. Clock generation circuitry receives a first clock signal at the first rate and produces the high rate signal for the processing device and the multiplexor. Clock generation circuitry includes sequentially connected delay devices, one connected to receive the first clock signal. Each delay device produces a trigger signal and an output signal a predetermined time after receiving the trigger signal from the previous delay device. A control circuit is common to the delay devices for controlling the predetermined time interval. An output circuit receives the output signals of the delay devices and produces the high rate clock signal.

Claims

1. An integrated circuit comprising:

a terminal connected to receive a first clock signal at a first rate, said first clock signal comprising a plurality of clock edges;

a multiplexor connected to receive a plurality of incoming data streams in parallel at said first rate under the control of said first clock signal, the multiplexor being controllable by a high rate clock signal to output that data serially at a second, higher rate;

a processing device coupled to receive data output from the multiplexor at the higher rate and controllable by said high rate clock signal to process that data; and

clock generation circuitry connected to receive said first clock signal at said first rate and operable to produce therefrom said high rate clock signal to be supplied to the processing device and to the multiplexor, wherein said clock generation circuitry is operable to produce, on receipt of each clock edge of the first clock signal, a predetermined number of clock edges to constitute said high rate clock signal whereby said high rate clock signal is synchronized with said first clock signal, said predetermined number being controllable to control a multiplication factor by which the high rate clock signal exceeds the first clock signal.

2. An integrated circuit as claimed in claim 1 wherein the clock generation circuitry comprises:

a plurality of sequentially connected delay devices, a first one of which is coupled to receive the first clock signal, each delay device being operable to produce a trigger signal and an output signal at a predetermined time after receiving a trigger signal from the previously connected delay device;

control circuitry operable to provide a common control signal to said delay devices for controlling said predetermined time interval; and

output circuitry coupled to receive the output signals of the delay devices to produce therefrom said second clock signal.

3. An integrated circuit as claimed in claim 2 in which the control circuitry is connected in a feedback loop so as to be responsive to an error signal resulting from comparison of the first clock signal with the trigger signal output by the last connected delay device.

4. An integrated circuit as claimed in claim 2 in which the output circuitry has a plurality of inputs for receiving respective ones of the output signals of the delay devices and is operable to change the state of its own output signal on receipt of each said output signal of the delay device.

5. An integrated circuit as claimed in claim 2 in which each delay device comprises analogue timing circuitry and digital control circuitry thereby to achieve a substantially linear response of the predetermined time interval to the control circuitry.

6. An integrated circuit as claimed in claim 5 in which the analogue timing circuitry comprises a controllable switch element responsive to a reset signal to change from a first state to a second state, a capacitive device connected to be charged up when said controllable switch element is in said first state, and a comparator connected to receive as a first input signal the voltage across the capacitive device, and as a second input signal said control voltage from said control circuitry, and producing as an output a timing signal in dependence on said first and second input signals and the digital control circuitry being connected to receive said timing signal and to provide in response thereto the trigger signal of the delay device and said reset signal.

7. An integrated circuit as claimed in claim 2 with p delay devices and circuitry for selecting n of the p delay devices (where n≦

p) for use in generation of the second clock signal.

8. An integrated circuit as claimed in claim 2 wherein the output circuitry for producing the second clock signal comprises a plurality of generation units connected respectively to receive the output signals of the delay devices, the generation units being individually connectable to a common output line and each generation unit having three states:

a neutral state in which the output line is examined;

a negative drive state in which a negative going pulse is driven onto the output line; and

a positive drive state in which a positive going pulse is driven onto the output line, the second clock signal thereby being generated on the output line as follows;

prior to receipt of a trigger signal by its associated delay device a generation unit is in its neutral state and when a delay device receives a trigger signal, the generation unit associated with that delay device responds to the output signal of that delay device to adopt one of its positive and negative drive states in dependence on the state of the second clock signal just prior to the change of state of that generation unit.

9. An integrated circuit as claimed in claim 3 wherein said output circuitry has a plurality of inputs for receiving respective ones of said output signals of said delay devices and is operable to change the state of its own output signal on receipt of each said output signal of the delay device.

10. An integrated circuit as claimed in claim 3 wherein each delay device comprises analog timing circuitry and digital control circuitry thereby to achieve a substantially linear response of the predetermined time interval to the control circuitry.

11. An integrated circuit as claimed in claim 1, in which the clock generation circuitry comprises circuitry for setting the ratio of the frequency of the high rate signal to the frequency of the first clock signal.

12. An integrated circuit as claimed in claim 11, in which the clock generation circuitry comprises a plurality of delay devices and wherein the circuitry for setting the ratio of the frequencies comprises circuitry for selecting from said plurality of delay devices of predetermined set thereof thereby to control said ratio.

13. A method of synchronizing a multiplexor and a processing device on an integrated circuit, the method comprising the steps of:

controlling a stream of data supplied to the multiplexor with a first clock signal at a first rate;

supplying the first clock signal to clock generation circuitry on the integrated circuit, said clock generation circuitry being operable to produce from said first clock signal a high rate clock signal which is an integral multiple of said first rate and synchronized thereto; and

controlling the multiplexor using the high rate clock signal.

14. A method of synchronizing a multiplexor as claimed in claim 13 further comprising the step of programming the ratio of the frequency of the high rate clock signal to the frequency of the first clock signal.

15. An integrated circuit comprising:

a terminal connected to receive a first clock signal at a first rate;

clock generation circuitry connected to receive said first clock signal at said first rate and operable to produce therefrom a high rate clock signal which is an integral multiple of said first rate and synchronized with said first rate;

a multiplexor having a plurality of inputs connected to receive respective incoming data streams in parallel under the control of said first clock signal at said first rate, the multiplexor being connected to receive said high rate clock signal and to output said data serially at the rate of said high rate clock signal; and

a processing device coupled to receive said data output from the multiplexor at the rate of said high rate clock signal and having a terminal for receiving said high rate clock signal to control processing of that data.