Interference canceller with feedforward transversal filter having switched tap-gain coefficients

• US 5,345,476 A
• Filed: 04/09/1993
• Issued: 09/06/1994
• Est. Priority Date: 04/09/1992
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Tsujimoto, Ichiro
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Webster, Bryan
• Application Number:
  US08/045,555
• Time in Patent Office: 515 Days
• Field of Search: 375/11, 375/12, 375/13, 375/14, 375/15, 375/16, 375/99, 364/724.19, 364/724.2, 333/18
• US Class Current: 375/233
• CPC Class Codes: H04B 1/123 using adaptive balancing or compensation means adaptive filter circuits and algorithms H03H

Abstract

An adaptive feedforward equalizer (12) has switched (N-1) tap-gain coefficients and a fixed tap-gain coefficient for the reference delay-line tap to operate on an incoming IF or baseband signal according to a first error signal (ε₁) representative of the difference between the input and output of a decision circuit (15). All tap-gain coefficients are active in the absence of an interference from an undesired source to cancel precursor distortion. The (N-1) tap-gain coefficients are nullified when such an interference is detected to reduce its precursor-cancelling capability. A first feedback equalizer (17) operates on the output of the decision circuit according to the first error signal to cancel postcursor distortion. A second feedback equalizer (18) nonlinearly filters the output of the decision circuit according to a second error signal (ε₂) and generates an estimate of a desired component of the output of the feedforward equalizer. The outputs of the second feedback equalizer (18) and the feedforward equalizer (12) are combined to produce the second error signal, or an estimate of an undesired component of the output of the feedforward equalizer. In the presence of the interference, the desired component estimate (ε₂) is combined with the outputs of the feedforward equalizer (12) and the first feedback equalizer (17) to produce an equalized signal for coupling to the decision circuit.

Claims

1. An interference canceller comprising:

means for detecting an interference signal transmitted from an undersired source for generating a gate control signal when the interference signal is detected;

a feedforward equalizer for operating on a signal received by an antenna and producing an equalized feedforward output signal, said feedforward equalizer comprising (N-1) delay-line elements connected in series to define N delay-line taps for producing successively delayed versions of said received signal at said N delay-line taps, N multipliers for operating on the delayed signals at said delay-line taps, N correlators responsive to a first error control signal for modifying signals at said delay-line taps for respectively supplying tap-gain signals to said multipliers, summing means for combining outputs from said N multipliers into said equalized feedforward output signal, and means for nullifying the outputs of (N-1) ones of said N multipliers in response to said gate control signal;

a decision circuit for deriving a decision output signal from an equalized desired signal;

a first feedback equalizer for operating on decision output signals from said decision circuit in accordance with said first error control signal;

a second feedback equalizer for nonlinearly filtering decision output signals from said decision circuit in accordance with a second error control signal for generating an estimate of a desired component of said equalized feedforward output signal;

a first combiner for combining outputs from said second feedback equalizer and said feedforward equalizer and producing and supplying an estimate of an undesired component of said equalized feedforward output signal to said second feedback equalizer as said second error control signal;

a second combiner for combining outputs from said first combiner, said feedforward equalizer and said first feedback equalizer and generating said equalized desired signal for said decision circuit;

means responsive to a difference between the outputs of said second combiner and said decision circuit for generating said first error control signal for said feedforward equalizer and said first feedback equalizer; and

gate means for establishing a connection between the output of said first combiner and an input of said second combiner in response to the presence of said gate control signal and clearing said connection in response to the absence of said gate control signal.

2. An interference canceller as claimed in claim 1, wherein said first feedback equalizer comprises:

N delay-line elements connected in series to the output of said decision circuit to define N delay-line taps at the outputs of the N delay-line elements for producing N successively delayed versions of the decision output signal;

N multipliers for operating on the delayed decision output signals at said N delay-line taps;

N correlators responsive to said first error control signal for modifying signals at said N delay-line taps for respectively supplying tap-gain signals to said N multipliers; and

summing means for combining outputs from said N multipliers into a combined signal and supplying the combined signal to said second combiner.

3. An interference canceller as claimed in claim 1, wherein said second feedback equalizer comprises:

N delay-line elements connected in series to the output of said decision circuit to define (N+1) delay-line taps for producing (N+1) successively delayed versions of the decision output signal at said (N+1) delay-line taps;

(N+1) multipliers for operating on the delayed decision output signals at said (N+1) delay-line taps;

(N+1) correlators responsive to said second error control signal for modifying signals at said (N+1) delay-line taps for respectively supplying tap-gain signals to said (N+1) multipliers; and

summing means for combining outputs from said (N+1) multipliers into a combined signal and supplying the combined signal to said first combiner.

4. An interference canceller as claimed in claim 2, wherein said second feedback equalizer comprises:

N delay-line elements connected in series to the output of said decision circuit to define (N+1) delay-line taps for producing (N+1) successively delayed versions of decision output signal at said (N+1) delay-line taps;

(N+1) multipliers for operating on the delayed decision output signals of said (N+1) delay-line taps;

(N+1) correlators responsive to said second error control signal for modifying signals at said (N+1) delay-line taps for respectively supplying tap-gain signals to said (N+1) multipliers; and

summing means for combining outputs from said (N+1) multipliers into a combined signal and supplying the combined signal to said first combiner.