Visual frame buffer architecture

• US 5,345,554 A
• Filed: 06/19/1992
• Issued: 09/06/1994
• Est. Priority Date: 04/17/1992
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Lippincott, Louis A., Rutman, Serge
• Primary Examiner(s): Shaw, Dale M.
• Assistant Examiner(s): Tung, Kee M.
• Application Number:
  US07/901,434
• Time in Patent Office: 809 Days
• Field of Search: 395/135, 395/148, 395/153, 395/162, 395/164, 395/165, 395/166, 340/750, 340/798-800, 345/185, 345/196, 345/201, 345/203, 345/132, 345/133, 345/149
• US Class Current: 345/547
• CPC Class Codes: G09G 2340/125 wherein one of the images is motion video
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: G09G 5/397 Arrangements specially adapted for transferring the contents of two or more bit-mapped memories to the screen simultaneously, e.g. for mixing or overlay G09G5/02 takes precedence
• CPC Class Codes: H04N 5/44504 Circuit details of the additional information generator, e.g. details of the character or graphics signal generator, overlay mixing circuits

Abstract

An apparatus for processing visual data includes a first video random access memory (VRAM) for storing a first bit plane of visual data in a first format. A graphics controller is coupled to the first VRAM by a data bus and a storage bus. The apparatus is capable of receiving at least a second VRAM for storing at least a second bit plane of visual data in at least a second format different from the first format. The received VRAMs are coupled to the graphics controller by data and storage busses. The visual data stored on the VRAMs are merged into a pixel stream which is then converted to analog form by a digital to analog converter. Data transfer addresses are generated for each of the VRAMs simultaneously, sequentially or in overlapping timed relationship.

Claims

1. An apparatus for integrating a graphics subsystem display buffer with a video subsystem display buffer comprising:

(A) first storage means for storing a first bit plane of graphics data in a first format;

(B) a graphics controller coupled to said first storage means by a data bus and a storage bus;

(C) a second storage means for storing a second bit plane of video data in a second format different from said first format, said second storage means being coupled to said graphics controller by a data bus and a storage bus;

(D) means employing chroma keying for forming a merged pixel stream from said graphics data stored on said first storage means and said video data stored on said second storage means, wherein said graphics data and said video data represent images stored at different spatial resolutions;

(E) means for generating data transfer addresses of the same type for each of said storage means contemporaneously; and

(F) means, coupled to said graphics controller, for generating an analog signal representative of said merged pixel stream.

2. An apparatus for integrating a graphics subsystem display buffer with a video subsystem display buffer comprising:

(A) first storage means for storing a first bit plane of graphics data in a first format;

(B) a graphics controller coupled to said first storage means by a data bus and a storage bus;

(C) a second storage means for storing a second bit plane of video data in a second format different from said first format, said second storage means being coupled to said graphics controller by a data bus and a storage bus;

(D) means employing chroma keying for forming a merged pixel stream from said graphics data stored on said first storage means and said video data stored on said second storage means, wherein said graphics data and said video data represent images stored at different spatial resolutions;

(E) means for generating data transfer addresses of the same type for each of said storage means sequentially; and

(F) means, coupled to said graphics controller, for generating an analog signal representative of said merged pixel stream.

3. An apparatus for integrating a graphics subsystem display buffer with a video subsystem display buffer comprising:

(A) first storage means for storing a first bit plane of graphics data in a first format;

(B) a graphics controller coupled to said first storage means by a data bus and a storage bus;

(C) a second storage means for storing a second bit plane of video data in a second format different from said first format said second storage means being coupled to said graphics controller by a data bus and a storage bus;

(D) means employing chroma keying for forming a merged pixel stream from said graphics data stored on said first storage means and said video data stored on said second storage means, wherein said graphics data and said video data represent images stored at different spatial resolutions;

(E) means for generating data transfer addresses of the same type for each of said storage means in overlapping time relationship; and

(F) means, coupled to said graphics controller, for generating an analog signal representative of said merged pixel stream.

4. An apparatus for integrating a graphics subsystem display buffer with a video subsystem display buffer comprising:

(A) first storage means for storing a first bit plane of video data in a first format;

(B) a graphics controller coupled to said first storage means by a data bus and a storage bus;

(C) at least one additional storage means for storing at least one additional bit plane of graphics data in at least one additional format different form said first format, each of said at least one additional storage means being coupled to said graphics controller by a data bus and a storage bus;

(D) means for forming a merged pixel stream from said video data stored on said first storage means and said graphics data stored on said at least one additional storage means, wherein said graphics data and said video data represent images stored at equivalent spatial resolutions;

(E) means for generating data transfer addresses of different types for each of said storage means at substantially the same time; and

(F) means, coupled to said graphics controller, for generating an analog signal representative of said merged pixel stream.

5. An apparatus for integrating a graphics subsystem display buffer with a video subsystem display buffer comprising:

(A) first storage means for storing a first bit plane of video data in a first format;

(B) a graphics controller coupled to said first storage means by a data bus and a storage bus;

(C) at least one additional storage means for storing at least one additional bit plane of graphics data in at least one additional format different from said first format, each of said at least one additional storage means being coupled to said graphics controller by a data bus and a storage bus;

(D) means for forming a merged pixel stream from said video data stored on said first storage means and said graphics data stored on said at least one additional storage means, wherein said graphics data and said video data represent images stored at equivalent spatial resolutions;

(E) means for generating data transfer addresses of different types for each of said storage means sequentially; and

(F) means, coupled to said graphics controller, for generating an analog signal representative of said merged pixel stream.

6. An apparatus for integrating a graphics subsystem display buffer with a video subsystem display buffer comprising;

(A) first storage means for storing a first bit plane of video data in a first format;

(B) a graphics controller coupled to said first storage means by a data bus and a storage bus;

(C) at least one additional storage means for storing at least one additional bit plane of graphics data in at least one additional format different from said first format, each of said at least one additional storage means being coupled to said graphics controller by a data bus and a storage bus;

(D) means for forming a merged pixel stream from said video data stored on said first storage means and said graphics data stored on said at least one additional storage means, wherein said graphics data and said video data represent images stored at equivalent spatial resolutions;

(E) means for generating data transfer addresses of different types for each of said storage means in overlapping time relationship; and

(F) means, coupled to said graphics controller, for generating an analog signal representative of said merged pixel stream.

7. An apparatus for integrating a graphics subsystem display buffer with a video subsystem display buffer comprising:

(A) first storage means for storing a first bit plane of video data in a first format;

(B) a graphics controller coupled to said first storage means by a data bus and a storage bus;

(C) means for receiving at least one additional storage means for storing at least one additional bit plane of graphics data in at least one additional format different from said first format, each of said at least one additional storage means being coupled to said graphics controller by a data bus and a storage bus;

(D) means for forming a merged pixel stream from said video data stored on said first storage means and said graphics data stored on said at least one additional storage means, wherein said graphics data and said video data represent images stored at equivalent spatial resolutions;

(E) means for generating data transfer addresses of different types for each of said storage means contemporaneously; and

(F) means, coupled to said graphics controller, for generating an analog signal representative of said merged pixel stream.

8. An apparatus for integrating a graphics subsystem display buffer with a video subsystem display buffer comprising:

(A) first storage means for storing a first bit plane of video data in a first format;

(B) a graphics controller coupled to said first storage means by a data bus and a storage bus;

(C) means for receiving at least one additional storage means for storing at least one additional bit plane of graphics data in at least one additional format different from said first format, each of said at least one additional storage means being coupled to said graphics controller by a data bus and a storage bus;

(D) means for forming a merged pixel stream from said video data stored on said first storage means and said graphics data stored on said at least one additional storage means, wherein said graphics data and said video data represent images stored at equivalent spatial resolutions;

(E) means for generating data transfer addresses of different types for each of said storage means sequentially; and

(F) means, coupled to said graphics controller, for generating an analog signal representative of said merged pixel stream.

9. An apparatus for integrating a graphics subsystem display buffer with a video subsystem display buffer comprising:

(A) first storage means for storing a first bit plane of video data in a first format;

(B) a graphics controller coupled to said first storage means by a data bus and a storage bus;

(C) means for receiving at least one additional storage means for storing at least one additional bit plane of graphics data in at least one additional format different from said first format, each of said at least one additional storage means being coupled to said graphics controller by a data bus and a storage bus;

(D) means for forming a merged pixel stream from said video data stored on said first storage means and said graphics data stored on said at least one additional storage means, wherein said graphics data and said video data represent images stored at equivalent spatial resolutions;

(E) means for generating data transfer addresses of different types for each of said storage means in overlapping time relationship; and

(F) means, coupled to said graphics controller, for generating an analog signal representative of said merged pixel stream.