Method for manufacturing a semiconductor device and a semiconductor memory device

• US 5,346,834 A
• Filed: 03/03/1992
• Issued: 09/13/1994
• Est. Priority Date: 11/21/1988
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd.
• Inventors: Kimura, Shinichiro, Hiraiwa, Atsushi, Moniwa, Masahiro, Takeda, Eiji, Kaga, Toru, Hisamoto, Dai, Tanaka, Haruhiko
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): NGUYEN, TUAN H
• Application Number:
  US07/845,063
• Time in Patent Office: 924 Days
• Field of Search: 437/41, 437/48, 437/49, 437/51, 437/52, 437/60, 437/919, 148/DIG. 14
• US Class Current: 438/152
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76278 Vertical isolation by selective deposition of single crystal silicon, i.e. SEG techniques
• CPC Class Codes: H01L 21/8238 Complementary field-effect transistors, e.g. CMOS
• CPC Class Codes: H01L 21/8248 Combination of bipolar and field-effect technology
• CPC Class Codes: H01L 21/8249 Bipolar and MOS technology
• CPC Class Codes: H01L 29/1062 of charge coupled devices
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66954 with an insulated gate
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/31 having a storage electrode stacked over the transistor
• CPC Class Codes: Y10S 148/014 Capacitor

Abstract

An improved method for manufacturing an insulated gate field effect transistor is provided. As a first step, a silicon oxide film is grown on a silicon substrate, and a first silicon nitride film is deposited thereon. The first silicon nitrite film, the silicon oxide film and the silicon substrate are then etched using a resist pattern as a mask to form a silicon island which includes at least a part of the silicon substrate. A second silicon oxide film is then grown on the surface of the silicon substrate exposed by the second step, as well as on the surface of the silicon island, and a second silicon nitrite film is deposited thereon. The second silicon nitrite film is then etched to leave a portion of the second silicon nitrite film deposited on a side wall of the silicon island. After this, a third silicon oxide film is grown by thermal oxidation of the surface of the silicon substrate to electrically separate the silicon island from the silicon substrate. Next a gate electrode is formed on silicon island, followed by forming source and drain regions in the silicon island employing the gate electrode as a mask.

Claims

1. A method of manufacturing a semiconductor memory device comprising:

a first step of forming a trench in a surface silicon substrate and forming an insulating film on an inner wall of said trench up to a predetermined height;

a second step of packing a conductor layer into said trench up to the surface level of said silicon substrate;

a third step of growing a first silicon oxide film on said silicon substrate and on said conductor layer and depositing a first silicon nitride film thereon;

a fourth step of etching said first silicon nitride film, said first silicon oxide film, said silicon substrate and said conductor layer at least to the level of said predetermined height by employing a resist pattern as a mask to form a silicon island comprised of a part of said silicon substrate and a part of said conductor layer;

a fifth step of growing a second silicon oxide film on a surface of said silicon substrate exposed by said second step and on a surface of said silicon island, depositing a second silicon nitride film thereon, and etching said second silicon nitride film so as to leave a portion of said second silicon nitride film deposited on a side wall of said silicon island and deposited on a connection of said silicon island and said conductor layer,

a sixth step of growing a third silicon oxide film by thermal oxidation of the surface of said silicon substrate to separate electrically said silicon island from said silicon substrate; and

a seventh step of forming a gate electrode on said silicon island and forming a source region and drain region in said silicon island by employing said gate electrode as a mask.