Semiconductor chip assemblies and methods of making same

• US 5,346,861 A
• Filed: 04/09/1992
• Issued: 09/13/1994
• Est. Priority Date: 09/24/1990
• Status: Expired due to Term

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: Tessera, Inc. (Adeia Inc.)
• Inventors: Khandros, Igor Y., DiStefano, Thomas H.
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): Picardat, Kevin M.
• Application Number:
  US07/865,984
• Time in Patent Office: 887 Days
• Field of Search: 437/209, 437/211, 437/215, 437/217, 437/220, 357/70, 357/74, 357/80
• US Class Current: 438/15
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/822 the substrate being a semiconductor, using silicon technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/274 by blanket deposition of the material of the layer connector
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/0652 Bump or bump-like direct electrical connections from substrate to substrate
• CPC Class Codes: H01L 2225/06579 TAB carriers; beam leads
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing testing or measuring during manufacture or treatment H01L22/00; testing electrical properties or locating electrical faults G01R31/00
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/3164 the coating being a foil
• CPC Class Codes: H01L 23/49805 the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/4985 Flexible insulating substrates H01L23/49572 and H01L23/49855 take precedence
• CPC Class Codes: H01L 23/49861 Lead-frames fixed on or encapsulated in insulating substrates H01L23/4985, H01L23/49805 take precedence
• CPC Class Codes: H01L 24/27 : Manufacturing methods
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: H05K 2201/10378 : Interposers
• CPC Class Codes: Y10T 29/4913 : Assembling to base an electrical component, e.g., capacitor, etc.

Abstract

A semiconductor chip assembly is mounted to contact pads in a compact area array. An interposer is disposed between the chip and the substrate. The contacts on the chip are connected to terminals on the interposer by flexible leads extending through apertures in the interposer. The terminals on the interposer in turn are bonded to the contact pads on the substrate. Flexibility of the leads permits relative movement of the contacts on the chip relative to the terminals and the contact pads of the substrate and hence relieves the stresses caused by differential thermal expansion. The arrangement provides a compact structure similar to that achieved through flip-chip bonding, but with markedly increased resistance to thermal cycling damage.

Claims

1. A method of assembling a semiconductor chip comprising the steps of:

(a) assembling a flexible sheetlike dielectric interposer formed separately from the chip and having first and second surfaces to the chip so that a first surface of said interposer confronts a front surface of said chip, so that said first surface of said interposer bears on said front surface of said chip and so that a portion of said interposer overlies a contact pattern area encompassed by a pattern of contacts on the front surface of said chip; and

(b) connecting the contacts on said chip to terminals disposed on the second surface of said interposer within an area of said interposer overlying said contact pattern area by means of flexible leads so that such leads extend between the contacts and terminals through apertures in said interposer and so that each such terminal is moveable with respect to the associated contact.

2. A method as claimed in claim 1 wherein said interposer has said terminals positioned thereon prior to said step of assembling said interposer to said chip.

3. A method as claimed in claim 2 wherein said interposer also has said leads positioned thereon and connected to said terminals prior to said step of assembling said interposer to said chip.

4. A method as claimed in claim 1 wherein said step of connecting said contacts to said terminals includes the step of bonding said leads to said contacts on said chip in said apertures by inserting a tool through said apertures.

5. A method as claimed in claim 1 further comprising the step of testing the assembled chip and interposer after said step of connecting said terminals to said contacts, said testing step including the step of making temporary electrical connections to said terminals.

6. A method as claimed in claim 5 wherein said step of making said temporary electrical connections includes the step of pressing probes against said terminals, said interposer being complaint, said interposer being deformed during said pressing step.

7. A method as claimed in claim 1 further comprising the step of applying a dielectric encapsulant so as to cover said flexible leads after said leads are connected to said contacts on said chip.

8. A method as claimed in claim 7 wherein said step of applying an encapsulant is performed so that said encapsulant extends into said apertures in said interposer.

9. A method as claimed in claim 7 wherein said step of applying an encapsulant is performed by applying said encapsulant in discrete portions so as to cover the junctures of said leads with said contacts on said chip but leave said terminals exposed.

10. A method as claimed in claim 9 wherein said step of applying an encapsulant includes the steps of applying a layer of said encapsulant on said second surface of said interposer and forming holes in said layer so that said terminals are exposed in said holes.

11. A method as claimed in claim 1 further comprising the step of manipulating said assembled interposer and chip by said interposer.

12. A method as claimed in claim 11 wherein said interposer is provided in the form of a tape, said step of assembling said chip to said interposer being performed so as to assemble a plurality of chips to said tape, said step of manipulating said chip including the step of advancing said tape so as to convey said chips with said advancing tape.

13. A method as claimed in claim 1 wherein said assembling and connecting steps are performed while said chip is present in a wafer incorporating a plurality of chips so as to assemble said plurality of chips to a plurality of interposers and connect the contacts of each such chip to the terminals on one of said interposers.

14. A method as claimed in claim 13 further comprising the step of severing said plurality of chips from one another after said assembling step.

15. A method as claimed in claim 14 wherein said plurality of interposers are initially connected to one another and said severing step includes the step of severing said connected interposers from one another.

16. A method as claimed in claim 1 wherein a plurality of interposers are provided as a sheetlike assemblage, said assembling and connecting steps including the steps of assembling one chip to each interposer in said sheetlike assemblage and connecting each such chip to the contacts on the interposer assembled herewith.

17. A method as claimed in claim 1 further comprising the steps of assembling a substrate with said interposer so that contact pads on a top surface of said substrate confront the terminals on said interposer and bonding said terminals to said pads.

18. A method as claimed in claim 17 wherein said step of bonding said terminals to said pads on said substrate includes the step of fusing a mass of electrically conductive material between each said terminal and the associated one of said pads.

19. A method as claimed in claim 18 wherein said electrically conductive material is a solder, the method further comprising the steps of providing a flux for said solder so that said flux is present during said fusing step and removing said flux after said fusing step, said masses supporting said interposer and chip on said substrate so that there is a gap between said second surface of said interposer and the top surface of said substrate, said step of removing said flux including the step of applying a rinsing fluid in said gap.

20. A method of making a semiconductor connection component comprising the steps of:

(a) providing a sheetlike dielectric interposer having first and second surface and a plurality of apertures extending between said surfaces;

(b) laminating a conductive sheet to said second surface of said interposer, so that a first surface of said sheet confronts said second surface of said interposer and so that said sheet overlies said apertures;

(c) forming a resist pattern on a second surface of said sheet facing away from said interposer, said resist pattern including lead areas at least partially aligned with said apertures and terminal areas contiguous with said lead areas but not aligned with said apertures;

(d) applying a resist to the first surface of said conductive sheet in said apertures;

(e) contacting said conductive sheet with an etchant so that said etchant removes said conductive sheet except in said lead areas and said terminal ares; and

(f) removing said resists.

21. A method as claimed in claim 20 wherein said step of applying a resist to the first surface is performed by laminating a sheet of resist to said first surface of said interposer so that the resist of said sheet fills said apertures.