Digital signal processing apparatus

• US 5,347,480 A
• Filed: 04/27/1993
• Issued: 09/13/1994
• Est. Priority Date: 10/29/1991
• Status: Expired due to Term

• Current Assignee: RPX Corporation
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Nix, Michael A., Bartkowiak, John G., Asghar, Safdar M.
• Primary Examiner(s): Smith, Jerry
• Assistant Examiner(s): Ngo, Chuong D.
• Application Number:
  US08/053,959
• Time in Patent Office: 504 Days
• Field of Search: 364/736, 364/741, 364/751, 364/754
• US Class Current: 708/524
• CPC Class Codes: G06F 17/10 Complex mathematical operations function generation by table look-up G06F1/03; evaluation of elementary functions by calculation G06F7/544
• CPC Class Codes: G06F 7/5443 Sum of products for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification

Abstract

An apparatus for processing a received signal according to a digital signal processing algorithm having a multiplier and a limit and quantization circuit appropriately connected within the apparatus to permit operation of the multiplier and the limit and quantization circuit in parallel with logic processing by the apparatus. The address bus system of the apparatus is connected to the parallel-connected components and conveys instructions to the parallel-connected components, at least in part, by predetermined address information via the address bus system.

Claims

1. An apparatus for processing data according to a plurality of instructions;

the apparatus comprising;

a control means for controlling operation of the apparatus, said control means issuing said plurality of instructions in a bus system according to a predetermined program;

said issuing being effected in a plurality of clock cycles, no more than one instruction of said plurality of instructions being issued in any respective clock cycle of said plurality of clock cycles;

a plurality of logical processing means for operatively responding to said plurality of instructions to perform logical processing of data according to predetermined logical relationships;

each respective logical processing means of said plurality of logical processing means effecting said logical processing according to a respective said predetermined logical relationship;

each respective instruction of said plurality of instructions including a respective address information portion and a respective instruction information portion;

at least a portion of said respective address portion designating a respective logical processing means of said plurality of logical processing means as an identified logical processing means, at least a portion of said respective instruction information portion providing operational details regarding said respective predetermined logical relationship effected by said identified logical processing means;

said bus system establishing operative connection among said control means and said plurality of logical processing means;

said bus system including an address bus system and an instruction bus system;

said address bus system communicating said address information portions of said plurality of instructions, said instruction bus system communicating said instruction information portions of said plurality of instructions;

at least one selected set of said logical processing means comprising at least two said respective logical processing means operatively responding to at least a portion of at least one predetermined said respective address information portion to perform said logical processing of data.