Processor-based smart packet memory interface
First Claim
1. A processor-based packet memory interface for controlling a transfer of packet data between multiple communications channels and packet memory in a communications adapter using one or more requestor IDS, wherein each requestor ID is a unique reference number identifying a transmit or receive process, comprising:
- a processor, configured to reserve at least one block of memory in the packet memory, receive a pointer from the communications adapter, wherein said received pointer points to said at least one block of memory reserved by said processor, and to reserve said reserved block of memory to free the requestor ID so that the number of concurrent processes is not limited to the number of requestor ID'"'"'s that can be handled by the communications adapter; and
processor RAM, coupled to said processor, configured to store said pointer to said at least one block of memory in the packet memory and to temporarily store packet data for transfer between the communications channels and the communications adapter.
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Accused Products
Abstract
A processor-based packet memory interface for controlling the transfer of data between multiple communications channels and packet memory in a communications adapter is presented, where the communications adapter uses requestor IDs to identify transmit and receive processes. The processor-based packet memory interface is controlled by a microprocessor configured to perform read and write operations with the communications adapter. The microprocessor is further configured to reserve a plurality of blocks of memory in the packet memory so that the number of communications channels that can be supported is not limited to the number of requestor ID'"'"'s that can be handled by the communications adapter. The processor-based packet memory interface also includes RAM, for use by the microprocessor, to store pointers to reserved blocks of memory in the packet memory and to temporarily store packet data for transfer between the communications channels and the communications adapter.
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Citations
18 Claims
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1. A processor-based packet memory interface for controlling a transfer of packet data between multiple communications channels and packet memory in a communications adapter using one or more requestor IDS, wherein each requestor ID is a unique reference number identifying a transmit or receive process, comprising:
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a processor, configured to reserve at least one block of memory in the packet memory, receive a pointer from the communications adapter, wherein said received pointer points to said at least one block of memory reserved by said processor, and to reserve said reserved block of memory to free the requestor ID so that the number of concurrent processes is not limited to the number of requestor ID'"'"'s that can be handled by the communications adapter; and processor RAM, coupled to said processor, configured to store said pointer to said at least one block of memory in the packet memory and to temporarily store packet data for transfer between the communications channels and the communications adapter. - View Dependent Claims (2, 3, 4, 5)
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6. A method for interfacing a plurality of communications channels to a communications adapter having packet memory and an adapter bus and using one or more requestor IDs, wherein each requestor ID is a unique reference number identifying a transmit or receive process, comprising the steps of:
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(a) receiving packet data from a plurality of communications channels; (b) storing received packet data in the packet memory, comprising the steps of (i) reserving a block of memory in the packet memory, (ii) receiving and storing a buffer pointer from the communications adapter, wherein said pointer points to said at least one block of memory reserved in said step (i), and (iii) reserving said reserved block of packet memory such that an associated requestor ID is available for use by the communications adapter to identify an alternative block of packet memory, such that packet data can be received on a greater number of communications channels than can be designated by the communications adapter using the requestor IDs; (c) transferring packet data from the packet memory to a designated communications channel; and (d) using a buffer pointer to manage the transfer of packet data. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13, 14)
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15. A communications adapter capable of receiving packets of data from at least one of a plurality of communications channels, storing received packets, and transferring received packets to at least one of a plurality of communications channels, comprising:
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a packet memory, configured to store packets of data received from said plurality of communications channels; an adapter manager, coupled to said packet memory, configured to manage operations of the communications adapter; an adapter bus, coupled to said adapter manager, configured to transfer data to and from said packet memory; and a processor-based packet memory interface, comprising a processor, configured to reserve at least one block of memory in the packet memory, receive a pointer from the communications adapter, wherein said received pointer points to said at least one block of memory reserved by said processor, and to reserve said reserved block of memory to free the requestor ID, and processor RAM, coupled to said processor, configured to store said pointer to said at least one block of memory in the packet memory and to temporarily store packet data from transfer between the communications channels and the communications adapter. - View Dependent Claims (16, 17, 18)
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Specification