Data processing system having serial self address decoding and method of operation

• US 5,347,523 A
• Filed: 12/27/1993
• Issued: 09/13/1994
• Est. Priority Date: 03/02/1992
• Status: Expired due to Fees

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Moyer, William C., Bruce, William C. Jr., Khatri, Sunil P.
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): LE, DIEU MINH T
• Application Number:
  US08/174,960
• Time in Patent Office: 260 Days
• Field of Search: 371/22.3, 371/11.3, 371/15.1, 371/22.1, 371/25.1, 371/17, 371/20.4, 371/20.5, 371/20.6, 371/29.1, 371/22.6, 371/21.1, 371/72, 395/200, 375/25, 375/27, 375/94, 324/73 R, 324/158 R, 364/926.1, 364/927.9
• US Class Current: 714/730
• CPC Class Codes: G01R 31/318552 Clock circuits details
• CPC Class Codes: G01R 31/318558 Addressing or selecting of subparts of the device under test
• CPC Class Codes: G01R 31/31858 Delay testing

Abstract

A data processing system (90) having a serial scan circuit (10). The serial scan circuit (10) has an address detector (12) for detecting and decoding M serially-provided address bits. Coupled to the address detector (12) is a clock generator (14) which is used for providing at least one derived clock signal. Coupled to the address detector (12) and the clock generator (14) is a serial scan chain (16) which is used to store N serially-provided data bits. A plurality of serial scan chains (10) is connected in a parallel configuration and used to form the data processing system (90). The M address bits and the N data bits are serially provided via a single conductor (24) in a time division multiplexed operation. Integrated circuit surface area is reduced by avoiding large address and data buses, and bus routing.

Claims

1. In a data processing system, a serial self-address decoding circuit used for serially receiving address and data, comprising:

means for address detecting, said means having a first input for serially receiving M address bits from a serial communication conductor within the data processing system, where M is an integer, a second input for receiving a system clock signal, and an output for providing an address match signal indicating detection of receipt of a predetermined binary address from the serial communication conductor;

a means for clock generation having a first input coupled to the output of the means for address detecting, a second input for receiving the system clock signal, and an output for selectively providing at least one control clock signal in response to both the address match signal and the system clock signal, the means for clock generation being enabled when the address match signal is asserted and being disabled when the address match signal is deasserted; and

a storage means having at least one clock input coupled to the at least one control clock signal, a second input coupled to the same serial communication conductor which is used to receive the M address bits, the serial communication conductor being used to serially transmit a first set of N data bits separate from the M address bits, where N is an integer, the serial communication conductor being time division multiplexed to serially provide both the M address bits to the means for address detecting, in a first time interval, and the first set of N data bits to the storage means, in a second time interval, wherein the first and second time intervals do not overlap, said storage means selectively storing the first set of N data bits in response to a predetermined M address bits being received by the means for address decoding and in response to the at least one control clock signal, and having an output for concurrently serially providing a second set of N data bits in response to the at least one control clock signal.

2. The serial scan circuit of claim 1 further comprising:

means for writing coupled to the storage means, the means for writing having N parallel outputs coupled to a third input of the storage means, said means for writing selectively altering the first set of N data bits stored in the storage means.

3. The serial scan circuit of claim 1 wherein the means for clock generation generates first and second non-overlapping control clock signals as the at least one control clock signal to control the storage of the first set of N data bits by the storage means, the first and second clock non-overlapping signals being respectively coupled to a first clock input and a second clock input of the storage means wherein the first and second clock inputs form the at least one clock input, the first and second non-overlapping control clock signals controlling the serial clocking of the first set of N data bits into the storage means and controlling the storage means to serially provide the second set of N data bits at the output of the storage means.

4. The serial scan circuit of claim 1 further comprising:

an enable circuit coupled to the storage means, the enable circuit coupling the second set of N data bits from the output of the storage means to an output terminal in response to the address match signal.

5. The serial scan circuit of claim 4 wherein the data processing system further comprises a plurality of serial scan circuits, each according to the serial scan circuit of claim 4, an output terminal of each serial scan circuit being electrically connected together, each serial scan circuit being connected to the serial communication conductor for receiving the M address bits and subsequently selectively storing the first set of N data bits.

6. The serial scan circuit of claim 4 wherein the data processing system further comprises a plurality of serial scan circuits, each according to the serial scan circuit of claim 4, an output terminal of each serial scan circuit being electrically connected together, each serial scan circuit being connected to the serial communication conductor for receiving a first predetermined number of M address bits and subsequently selectively receiving N data bits, wherein the numerical value of N may vary between each of the serial scan circuits in the plurality of serial scan circuits.

7. The serial scan circuit of claim 6 wherein the data processing system comprises a plurality of serial scan circuits, each of the serial scan circuits formed in accordance with claim 6, wherein the plurality of serial scan circuits contains from two to 2^M serial scan circuits connected in parallel.

8. The serial scan circuit of claim 1 wherein the storage means further comprises an N-bit serial shift register circuit.

9. The serial scan circuit of claim 1 wherein the means for address detecting is an M-bit serial shift register circuit.

10. In a data processing system, a method of self-address decoding within a serial scan circuit in a serial manner, the method comprising the steps of:

providing data on a serial communication conductor wherein the serial communication conductor provides both M address bits and N data bits, where M and N are integers, the M address bits being provided in a different time interval than the N data bits;

serially receiving the M address bits from the serial communication conductor;

detecting whether the M address bits match a predetermined address value;

providing an address match signal indicating detection of receipt of the predetermined address value from the serial communication conductor;

receiving a system clock signal of the data processing system;

enabling a clock generator in response to the address match signal to provide at least one control clock signal in response to both the address match signal and the system clock signal; and

serially receiving and selectively storing N data bits in a storage means of the serial scan circuit in response to the at least one control clock signal, and concurrently serially providing at an output of the serial scan circuit the N data bits in response to the at least one control clock signal, the N data bits being provided by the serial communication conductor in a time period after the receipt of the M address bits.

11. The method of claim 10 further comprising the step of:

selectively altering the N data bits in the storage means to a predetermined binary value.

12. The method of claim 10 further comprising the step of:

resetting the data processing system to initialize the data processing system prior to the step of receiving the M address bits.

13. The method of claim 10 further comprising the steps of:

providing a plurality of serial scan circuits, each serial scan circuit being coupled in parallel and having an address detector for receiving the M address bits from the serial communication conductor;

serially scanning N data bits from thru only a predetermined one of the serial scan circuits in response to the M address bits.

14. A serial scan circuit using M serially-provided address bits to permit storage of N serially-provided data bits wherein the M serially-provided address bits are self-decoded and M and N are integers, the serial scan circuit comprising:

an address detector circuit having a first input connected to a serial communication conductor for receiving the serially provided M address bits, a second input for receiving a system clock signal, and an output for providing an address match signal indicating detection of receipt of a predetermined binary address from the serial communication conductor;

a clock generator circuit having a first input coupled to the output of the address detector circuit for receiving the address match signal, a second input for receiving the system clock signal, and an output for providing a control clock signal in response to both the address match signal and the system clock signal; and

a serial scan chain of flip-flop circuits having a first input coupled to the control clock signal, a second input coupled to the serial communication conductor for serially receiving N data bits only if the predetermined binary address is received by the address detector circuit, the serial communication conductor being configured to serially provide both the M address bits and the N data bits, said serial scan chain of flip-flop circuits selectively storing the N data bits in response to the control clock signal, and having an output for concurrently serially providing the N data bits in response to the control clock signal.

15. The serial scan circuit of claim 14 further comprising:

a parallel writing circuit coupled to the serial scan chain of flip-flops, the parallel writing circuit having a predetermined number within a range of one to N of parallel outputs for altering at least a portion of the N serially-provided data bits stored in the serial scan chain of flip-flops.

16. The serial scan circuit of claim 14 further comprising:

an enable circuit having an input coupled to the output of the serial scan chain of flip-flops coupling the N data bits to an output terminal thereof in response to the address match signal.

17. The serial scan circuit of claim 16 further comprising:

a plurality of serial scan circuits, each according to the serial scan circuit of claim 16, the output terminal of each serial scan circuit being electrically connected together, each serial scan circuit being connected to the serial communication conductor for receiving the M address bits and subsequently selectively storing the N data bits.

18. The serial scan circuit of claim 16 further comprising:

a plurality of serial scan circuits, each according to the serial scan circuit of claim 16, the output terminal of each serial scan circuit being electrically connected together, each serial scan circuit being connected to the serial communication conductor for receiving a first predetermined number of address bits and subsequently selectively receiving a second predetermined number of N data bits, the second predetermined number of N data bits varying in value between each of the serial scan circuits.

19. The serial scan circuit of claim 18 wherein the plurality of serial scan circuits comprises 2^M or less serial scan circuits.

20. In a data processing system, a plurality of serially coupled storage devices forming a serial scan circuit, the serial scan circuit having serial address decoding wherein a serially provided bit stream of M address bits addresses the serial scan circuit, the serial scan circuit comprising:

a means for address detecting having a first input for serially receiving the M address bits from a single serial communication conductor within the data processing system, where M is an integer, a second input for receiving a system clock signal, and an output for providing an address match signal indicating detection of receipt of a predetermined binary address from the serial communication conductor;

a means for input control coupled to the means for address detecting and having a first input coupled to the single serial communication conductor, a second input for receiving the address match signal, and an output for selectively providing a first set of N serial data bits received via the single serial communication conductor, where N is an integer;

a storage means having a first input coupled to at least two control clock signals, a second input coupled to the output of the means for input control for serially receiving the first set of N data bits, the serial communication conductor being time division multiplexed to serially provide both the M address bits and the first set of N data bits, said storage means selectively storing the first set of N data bits in response to the at least two control clock signals, and having an output for concurrently serially providing a second set of N data bits in response to the at least one control clock signal; and

means for output control coupled to the storage means for serially receiving the second set of N data bits and transmitting the N data bits via an output conductor in response to the address match signal.

21. A data processing system for serially receiving and processing I serial bits of data, the data processing system comprising:

a single serial communication conductor used for providing I serial bits of data to the data processing system, wherein the I serial bits of data include M serially provided address bits and N serially provided data bits, where I, M, and N are positive integers and I is equal to (N plus M);

a system clock conductor for providing a system clock signal;

an address detector having a first input coupled to the system clock conductor, a second input coupled to the single serial communication conductor, and an output for providing a control signal, the address detector decoding the M serially provided address bits and selectively asserting the control signal in response to receiving M serially provided address bits which indicate a predetermined binary address value; and

a plurality of storage devices having a first input coupled to the single serial communication conductor, a second input for receiving a serial scan clock wherein the serial scan clock is enabled only if the predetermined binary address is received by the address detector, and an output for providing serial output data, one of the plurality of storage devices storing the N bits of serially provided data in response to the assertion of the control signal.

22. A data processing system having a plurality of self-address decoding serial scan circuits comprising:

a first self-address decoding serial scan circuit comprising;

a first address detection circuit having a first input coupled to a system clock conductor, a second input coupled to a single serial communication conductor, and an output for providing a control signal, the first address detector circuit decoding M serially provided address bits which are provided by the single serial communication conductor and selectively asserting the control signal in response to receiving M serially provided address bits which indicate a predetermined binary address value;

a first clock generation circuit having an input for receiving the control signal from the first address detection circuit and an output for providing a first selective clock signal, the first selective clock signal functioning only if the control signal is asserted; and

a first serial data storage device having an input for receiving the first selective clock signal and an input coupled to the single serial communication conductor for receiving N serially provided data bits after the M serially provided address bits are received, the N serially provided data bits being stored by the first serial data storage device only if the first selective clock signal is functioning in response to the control signal of the first address detection circuit;

a second self-address decoding serial scan circuit coupled in parallel to the first self-address decoding serial scan circuit, the second self-address decoding serial scan circuit comprising;

a second address detection circuit having a first input coupled to a system clock conductor, a second input coupled to a single serial communication conductor, and an output for providing a second control signal, the second address detector circuit decoding M serially provided address bits which are provided by the single serial communication conductor and selectively asserting the second control signal in response to receiving M serially provided address bits which indicate a predetermined binary address value;

a second clock generation circuit having an input for receiving the second control signal from the second address detection circuit and an output for providing a second selective clock signal, the second selective clock signal functioning only if the second control signal is asserted; and

a second serial data storage device having an input for receiving the second selective clock signal and an input coupled to the single serial communication conductor for receiving N serially provided data bits after the M serially provided address bits are received, the N serially provided data bits being stored by the second serial data storage device only if the second selective clock signal is functioning in response to the control signal from the second address detection circuit.